CONTENT OF THE ASIAN IBIS OPEN FORUM SUMMIT MEETING
November 13, 2012
Hsinchu, Taiwan

   .zip  Compressed
   .ppt, .pps  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text
   .jpg  Pictures

ADMINISTRATIVE DOCUMENTS:

00readme.txt     This Document

a111312.txt        Agenda
m111312.pdf        Minutes

announcement_chinese.pdf  Announcement, Traditional Chinese

CONFERENCE RECORD:

cover.pdf          Cover Page
booklet.pdf        Conference booklet of presentations

cover.ppt          Original Files for editing
cover_poster.ppt


PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):


pytel1.pdf    Electronic Interconnect Challenges
              Steve Pytel (ANSYS, USA)

mirmak.pdf    IBIS 5.1 An Overview 
              Michael Mirmak (Intel Corporation, USA)
              [Presented by Lance Wang (IO Methodology, USA)]

liu_p.pdf     Using Latency Insertion Method to Handle IBIS Models
              Ping Liu*#, Jilin Tan*##, and Jose Schutt-Aine**
              (*Cadence Design Systems, #PRC, ##USA and
              **University of Illinois, USA)
              [Presented by Joseph Kao (Cadence Design Systems, ROC)]

hsuan.pdf     IBIS-AMI, Industry Adoption and Current Challenges
              Naijen Hsuan and TingHao Yeh (ANSYS, ROC)
              [Presented by Naijen Hsuan (ANSYS, ROC)]

liu_jt.pdf    Efficient End-to-end Simulations of 25G Optical Links
              Jing-Tao Liu*#, Fangyi Rao*##, Sanjeev Gupta** and
              Amolak Badesh** (*Technologies, #PRC, ##USA; and
              **Avago Technologies, USA)
              [Presented by Ming-Chih Lin (Agilent Technologies, ROC)]

lin.pdf       Chip PDN Model for Power Aware Signal Integrity Analysis
              Jack W.C. Lin# and Raymond Y. Chen##
              (Cadence Design Systems, #ROC, ###USA)
              [Presented by Jack W.C. Lin (Cadence Design Systems, ROC)]

ross.pdf      IBIS Parser Update
              Bob Ross (Teraspeed Consulting Group, USA)
              [Presented by Anders Ekholm ( Ericsson, Sweden)]

wang.pdf      IBIS Validation Method Review
              Lance Wang (*IO Methodology, USA)

pytel2.pdf    The Evolution of DDR Memory and Overcoming Challenges
              of DDR3/4 Design
              Steven Pytel (ANSYS, USA)

Kukal.pdf     Designing DDR3 System Using Static Timing Analysis in
              Conjunction with IBIS Simulations
              Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek###
              (Cadence Design Systems, #India, ##China, ###Germany)
              [Presented by Kent Ho (Cadence Design Systems, ROC)]