CONTENT OF THE ASIAN IBIS OPEN FORUM SUMMIT MEETING
November 16, 2012
Yokohama, Japan

   .zip  Compressed
   .ppt, .pps  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text
   .jpg  Pictures

ADMINISTRATIVE DOCUMENTS:

00readme.txt     This Document

a111612.txt           Agenda
m111612.pdf           Minutes


PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):


mirmak.pdf    IBIS 5.1 An Overview 
              Michael Mirmak (Intel Corporation, USA)
              [Presented by Lance Wang (IO Methodology, USA)]

ross.pdf      IBIS Parser Update
              Bob Ross (Teraspeed Consulting Group, USA)
              [Presented by Anders Ekholm (Ericsson, Sweden)]

maeda.pdf     S-Parameter: What You Can Read, What You Have To Read
              Shinichi Maeda (KEI Systems, Japan)

lin.pdf       Chip PDN Model for Power Aware Signal Integrity Analysis
              Jack W.C. Lin# and Raymond Y. Chen##
              (Cadence Design Systems, #Taiwan, ##USA)
              [Presented by Yukio Masuko
              (Cadence Design Systems, Japan)]

kibe.pdf      The Voice from Practical Designing with SI Simulation
              Hironari Kibe (Zuken, Japan)

wang.pdf      IBIS Validation Method Review
              Lance Wang (*IO Methodology, USA)

torigoshi.pdf 
              Over-clocking Model Validation
              Yasuki Torigoshi (Toshiba, Japan)

kukal.pdf     Designing DDR3 System Using Static Timing Analysis in
              Conjunction with IBIS Simulations
              Taranjit Kukal#, Zhangmin Zhong##, and Heiko Dudek###
              (Cadence Design Systems, #India, ##China, ###Germany)
              [Presented by Hirotsugu Ueno
              (Cadence Design Systems, Japan)]

matsumura.pdf
              The Application of Simulation Kit Using USB3.0 IBIS-AMI
              Model
              Motoaki Matsumura (Fujitsu Semiconductor, Japan)