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       A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:00 - 16:30, Monday November 17, 2014

Location:   Sherwood Hotel
            111 Min Sheng E Road
            Sec.3, Taipei, Taiwan

Rooms:      Ballrooms 3F (3rd Floor, look for signs)

Primary Sponsor
            Intel Corporation

Sponsors:   ANSYS
            Cadence Design Systems
            IO Methodology
            Synopsys

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          I B I S  S U M M I T  M E E T I N G  A G E N D A

8:15    SIGN IN
          - Vendor Tables Open at 8:30

9:00    Welcome
          - Michael Mirmak
            (Chair IBIS Open Forum, Intel Corporation, USA)

9:10    Activities and Direction of IBIS
          Michael Michael (Intel Corporation, USA)

9:35    Handling of Overclocking Caused by Delay in Waveform
        Tables
          Radek Biernacki*, Ming Yan*, Randy Wolff**
          Justin Butterfield**
          (*Keysight Technologies, **Micron Technology, USA)

10:05   Differential Buffer Using IBIS Models for PDN
        Simulations
          Lance Wang (IO Methodology, USA)

10:35   BREAK (Refreshments and Vendor Tables)

10:55   True Differential IBIS Model for SerDes Analog Buffer
          Shivani Sharma, Tushar Malik, Taranjit Kukal
          (Cadence Design Systems, India)

11;30   IBIS AMI Validation
          Zilwan Mahmod, Anders Ekholm (Ericsson, Sweden)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)
          - Vendor Tables

13:30   Signing IBIS Model Against DDR4 Spec
          Tushar Malik, Taranjit Kukal
          (Cadence Design Systems, India)

14:10   Corner Considerations
          Bob Ross (Teraspeed Labs, USA)

14:45   BREAK (Refreshments and Vendor Tables)

15:05   Best Practices for High-Speed Serial Link Simulation
          Minggang Hou (ANSYS, China)

15:55   CONCLUDING ITEMS

16:30   END OF IBIS SUMMIT MEETING

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