------------------------------------------------------------------ A S I A N I B I S S U M M I T I N F O R M A T I O N Time/Date: Friday, November 17, 2017, 13:30 to 17:30 Meeting starts at 13:30 Location: Akihabara UDX Bldg. 4-14-1, Sotokanda, Chiyoda-Ku Tokyo 101-0021, JAPAN URL: Akihabara UDX Building (Japanese) http://udx.jp/ Akihabara UDX Building in the Akihabara Crossfield Conference Center (English) http://www.akiba-cross.jp/english/ Room: 4F NEXT2 Organizational Sponsors: Japan Electronics and Information Technology Industries Association (JEITA) IBIS Open Forum Sponsors: ANSYS, Inc. Cadence Design Systems Cybernet Systems Keysight Technologies Ricoh Toshiba Corporation Zuken, Inc. ------------------------------------------------------------------ I B I S S U M M I T M E E T I N G A G E N D A 13:30 SIGN IN 13:35 MEETING WELCOME Mitsuharu UMEKAWA (Keysight Technologies, Japan) Chair, JEITA EDA Model Specialty Committee Mike LaBONTE (SiSoft, USA) Chair, IBIS Open Forum 13:45 IBIS Update Mike LaBONTE (SiSoft, USA) 14:10 What's Expected for IBIS-AMI from the Perspective of End-User Support Masao NAKANE (Xilinx, Japan) 14:40 DDR System Simulation: What Issue to Simulate Shinichi MAEDA (KEI Systems, Japan) 15:10 BREAK 15:30 Investigation of the Package Crosstalk Noise to DDR4-IF Signal by IBIS [Define Package Model] Akiko TSUKADA, Masaki KIRINAKA (Fujitsu Interconnect Technologies Limited, Japan) [Presented by Akiko TSUKADA (Fujitsu Interconnect Technologies Limited, Japan) 16:15 On die De-cap Modeling Proposal Kazuki MURATA (Ricoh Company, Japan) 16:40 Interconnect Modeling Update Using IBIS-ISS and Touchstone Michael MIRMAK (Intel Corporation, USA) [Presented by Mike LaBONTE (SiSoft, USA)] 17:15 CONCLUDING ITEMS 17:30 END OF MEETING ----------------------------------------------------------------