CONTENT OF THE ASIAN IBIS OPEN FORUM SUMMIT MEETING
October 27, 2006
Shanghai, China

   .zip  Compressed
   .ppt, .pps  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text
   .jpg  Pictures

ADMINISTRATIVE DOCUMENTS:

00readme.txt   This Document

a102706.txt    Agenda
m102706.txt    Minutes

announcement_chinese.pdf  Announcement, Traditional Chinese

CONFERENCE RECORD:

cover.pdf      Cover Page
booklet.pdf    Conference booklet of presentations


PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):

mirmak.zip     The Direction of IBIS as a Standard (.ppt)
mirmak.pdf     Mirmak, Michael (Intel Corporation, USA)

zheng.zip      IBIS Model Validation Report (.ppt)
zheng.pdf      Zheng, Qi (Fiberhome Telecommunications Technology, China)

kusunoki.zip   IBIS Model Engineering for SI Analysis (.ppt)
kusunoki.pdf   Kusunoki, Kazuhiko (Cybernet Systems, Japan)

wang.pdf       Case Study: Spice Macromodeling for PCI Express Using
               IBIS 4.2
               Wang, Lance (Cadence Design Systems, USA)

katz.pdf       System-Level Timing Closure Using IBIS Models
               Katz, Barry, (Signal Integrity Software (SiSoft), USA)

huang.zip      Statistical Eye Simulaton Requirements (.ppt)
huang.pdf      Huang, ChunXing (Huawei Technologies, China) 

byers.pdf      Methodologies for Multi-Gigabit Interconnect Design
               Byers, Andy, and Williams, Lawrence (Ansoft Corporation,
               USA)
               Presented by Byers, Andy, (Ansoft Corporation, USA)

chitwood.pdf   System-Level SSO Simulation Techniques with Various IBIS
               Package Models
               Chitwood, Sam*, Lin, Jack, W.C.**, and Chen, Raymond Y.*
               (Sigrity, *USA and **China)
               Presented by Chen, Raymond Y. (Sigrity, USA)

zhu.pdf        Using S-parameters for Behavioral Interconnect Modeling 
               Zhu, ShunLin, (ZTE Corporation, China)

watanabe.zip   JEITA EDA - WG Activity and Study of Interconnect Model
watanabe.pdf   Part-3 (.ppt)
               Watanabe, Takeshi*, Ikeda, Hiroaki**, and JEITA (*NEC
               Electronics, **Japan Aviation Electronics, Japan)
               (Note, this version is presented at the meeting and
               expanded from the version used in the Conference Record)
               Presented by Watanabe, Takeshi (NEC, Japan)

dodd1.zip      IBIS 4.2 and VHDL-AMS for Serdes and DDR2 Analysis (.ppt
dodd1.pdf      with some notes)
               Dodd, Ian and Pratt, Gary (Mentor Graphics Corporation,
               USA)
               Presented by Dodd, Ian (Mentor Graphics Corporation, USA)

dodd2.zip      IBIS Modeling of DDR2 in Conjunction with Linear Channel
dodd2.pdf      Analysis (.ppt)
               Dodd, Ian (Mentor Graphics Corporation, USA)

ross.zip       ODT, Pre-Emphasis, and Speed (.ppt)
ross.pdf       Ross, Bob (Teraspeed Consulting Group, USA)