DATE: 11/05/06 SUBJECT: October 27, 2006 EIA IBIS Open Forum Summit Minutes GEIA BALLOT ELIGIBILITY (Must have attended 2 of the last 3 meetings, including Summits) Member GEIA Eligible (A = Active) -2 -1 Current Meeting ---------------------------------------------------------------- Cadence A X X Cisco A X X Green Streak Programs A X X Intel A X X X LSI Logic Mentor Graphics A X X X Micron Technology A X X NEC X Siemens AG A X Signal Integrity Software X Sigrity X Synopsys X Teraspeed Consulting Group A X X X Texas Instruments X ZTE X VOTING MEMBERS AND 2006 PARTICIPANTS Agere (Nirav Patel) Agilent Sanjeev Gupta, Nilesh Kamdar AMD [Wasim Ullah], Tadashi Arai Apache Design Solutions Ji Zheng Applied Simulation Technology Fred Balistreri Cadence Design Systems Lance Wang*, Lanbing Chen*, Wenliang Dai*, Jinbai Liu*, John Peng*, Coco Xu*, Lily Yang*, WenJian Zhang*, Alex Zhao*, Weiran Zhao*, Zhangmin Zhong*, George Zhou* Cisco Systems Syed Huq, Mike LaBonte, AbdulRahman Rafiq, Pedo Miran, Salman Jiva, Gurpreet Hundal, Todd Westerhoff Fluent (Chetan Desai) Freescale (Jon Burnett) Green Streak Programs Lynne Green Hitachi ULSI Systems Kazuyoshi Shoji Integrated Circuit Systems (ICS) (Dan Clementi) Intel Corporation Michael Mirmak*, Arpad Muranyi, Stephen Peters, Vishram Pandit, Junyong Deng*, Haifeng Gong*, Guobing Han*, Tao Hu*, Karen Kang*, Kuen Yew Lam*, Fanghui Li*, Dan Liu*, Albert Mu*, Zefeng Ni*, Jirong Wang*, Mingchang Wang*, Even Wu*, Fan Xia*, Baoshu Xu*, Jiannan Xu*, Long Yang*, Maoxin Yin*, Xiangyin Zeng*, Kevin Zhang*, Xinjun Zhang*, Zheli Zhang* LSI Logic Frank Gasparik, Kim Helliwell, Praveen Soora Mentor Graphics John Angulo, Ian Dodd*, Gary Pratt, John Shields, Simon Vines, [Guy de Burgh], Simon Hou*, Baolong Li*, Nan Liao*, Xuefeng Liu*, Yan Liu*, Vivian Pan*, Danny Perng*, HaoLei Zhu*, Micron Technology Randy Wolff NEC Electronics Corporation Takeshi Watanabe* Samtec (Corey Kimble) Siemens AG Eckhard Lenski, Manfred Maurer, Katja Koller, Klaus Huebner, Heinz-Hartmut Ibowski, Flavio Maggioni, Roberto Preatoni Siemens Medical [David Lieby] Signal Integrity Software Barry Katz*, Douglas Burns, Mike Mayer Walter Katz, Kevin Fisher Sigrity Sam Chitwood, Raymond Chen*, Xianfeng Li*, Jack Lin*, Jing Wang* Silego (Joe Froniewski) STMicroelectronics (Antonio Girardi) Synopsys Andy Tai*, Ted Mido, Xuefeng Chen*, Jinghua Huang*, Yan Luo*, ChangLei Zhang*, Qin Zhang* Teraspeed Consulting Group Bob Ross* Texas Instruments Otis Gorley, Richard Ward Toshiba Yasumasa Kondo, Yoshishiro Hamaji Motochika Okano Xilinx (Ray Anderson) ZTE Shunlin Zhu*, Bin Chen*, Huifeng Chen*, SonGrui Chen*, Xiaolin Chen*, Hui Jiang*, Gu Li*, Fuming Wu*, Lixian Yang*, Xiang Yao* Zuken Michael Schaeder, Ralf Bruening OTHER PARTICIPANTS IN 2006: Acro Information Technology Jimmy Zhong* Actel (Prabhu Mohan), Ann Lau Altera Khalid Ansari, David Lieby Amkor Technology Nozad Karim Ansoft Corporation Michael Brenneman, Andy Byers*, Song Deng*, Jack Qui*, Sally Wang* Apple Computer [Zhiping Yang] Ashenden Designs Peter Ashenden ATP Electronics Dan Li*, Charlie Liu* Atmel Corporation Pucheng Li* Beijing Institute of Technology Kun Deng* Betty TV Stephanie Goedecke Bosch Ingo Doerr, Jurgen Hasch Celestica Harrison Xue*, Jiang Zhu* China Integrated Circuit Shirley Hu* Centec Networks, Inc. Lifeng Qin*, Kai Zhao* CSIC Yongning Zai* Cybernet Systems (KAW) Kazuhiko Kusunoki*, Azusa Harada Toshiyo Saito, Keiji Soyama, Ady Deng*, David Ding*, Summer Li*, Golden Qian*, David Xu* Datang Mobile Communications Baisun Chen*, Jianchao Zhao* Equipment Dell Aubrey Sparkman East China Institute of Jian Pan* Computing Technology Eastern China Institute of Wen Dai*, Han Liao* Engineering EDN China Changli Ying*, Gang Yao* EFM Ekkehard Miersch Fiberhome Telecommunications Qi Zheng*, Jianchun Wan* Technology Foctel Jianchun Wan* Force10 Networks Robert Badal Free Electron Software Al Davis GEIA (Chris Denham) Global Engineering Solutions Zhenning Liao* HiSilicon Technologies Song Jun* Hong Jing Company Lia Song* Hongsi Qunhui Yu* Huawei Technologies Weidong Liu*, Zhang Chen*, Jin Hu*, Chungxing Huang*, Peng Huang*, Gongxian Jia*, Zhiwei Li*, Qiang Lei*, Yitong Wen*, Liang Wu*, Shengyu Wu*, Huawei Yang*, Zhoa Yi*, Yun Zhu* Huawei-3Com Technology Dingding Chen*, Huanyang Chen*, Zhongjian Chen*, Xinnian Duan*, Chunjiang Gu*, Cheng Li*, Xiaoqun Li*, Fuqiang Shi*, Guiwei Suo*, Bo Wang*, Wei Yang*, Haitao Zhang*, Wenhua Zhu*, Yuan Zhuang* IBM Lance Thompson Infineon Radovan Vuletic, Minka Gospodinova Christian Sporrer, Amir Motamedi Interactive Device Technology David Chen*, Andy Li*, Yuyang Wang*, Liang Xu* Inventec Corporation Zhong Peng*, Xiaoping Yang*, Yan Zhi* Japan Aviation Electronics Hiroaki Ikeda* JEITA Atshushi Ishikawa Jiangsu Automatics Institute Boxing Deng* Leventhal Design Roy Leventhal Lianchuang International Jason Wang* Advertising (EE Times China) Lynguent Andrew Levy Marvell (Itzik Peleg) NXP Semiconductors Sudarshan Honnudike* NCSU Paul Franzon Panasonic Atsuji Ito* Philips Herve Menager Politecnico di Torino Igor Stievano Rambus Nirmal Jain RadiSys Corporation Yiming Cheng*, Greg Fu*, Guangcao Fu*, Jeffrey Yang*, Siyuan Yang* Right Solution Industries Chao Chen*, Rudy Shi* Samsung Heeseok Lee, Il Seong Schneider Electric Gang Wu* Shanghai Jade Technologies Dunear Huang*, Howard Wang* Shanghai JiaoTong University Bin Chen*, Zhigang Hao*, Shijie Huang*, Feng Li*, Tongyu Peng*, Liu Wang* Xuehong Yu*, Kai Zhu* Shanghai Municipal Information Jing Lin* Commission Shanghai Silicon Intellectual Bulu Xu* Property Exchange SI Institute Chengfeng Weng* Silicon Image (Ook Kim) SimLab Heiko Grubrich Sinosun Technology Cui Peng* Tandem Consulting Jack Luo* Trident Multimedia Technologies Evelyn Cao* (Shanghai) Vectronix AG Luca Giacotto VeriSilicon Steven Guo*, Zhan Zhou* Via Technologies Jummy Hsu* Winnet Electronics Wenhao Liang*, Xin Xu*, Xigu Technology Zhiyuan Chen* In the list above, attendees at the meeting are indicated by *. Principal members or other active members who have not attended are in parentheses. Participants who no longer are in the organization are in square brackets. UPCOMING MEETINGS The bridge numbers for future IBIS teleconferences are as follows: Date Telephone Number Bridge # Passcode October 31, 2006 Asian IBIS Summit (Japan) - NO BRIDGE November 17, 2006 1-916-356-2663 3 676-3004 All meetings are 8:00 AM to 9:55 AM US Pacific Time. Meeting agendas are typically distributed seven days before each Open Forum. Minutes are typically distributed within seven days of the corresponding meeting. When calling into the meeting, provide the bridge number and passcode at the automated prompts. If asked by an operator, please request to join the IBIS Open Forum hosted by Michael Mirmak. For international dial-in numbers, please contact Michael Mirmak. NOTE: "AR" = Action Required. --------------------------------MINUTES----------------------------------- WELCOME AND INTRODUCTIONS The IBIS Open Forum Summit was held in Shanghai, PRC at the Radisson New World Hotel. About 172 people representing 52 organizations attended. The notes below capture some of the content and discussions. The meeting presentations and other documents are available at: http://www.eda-stds.org/summits/oct06a/ Danny Perng of Mentor Graphics provided translations to English and Chinese during the first part of the program. Lance Wang of Cadence Design Systems provided summary translations during the remainder of the agenda, except where noted. Weidong Liu of Huawei opened the Summit meeting by thanking the participants and noting the relationship of Huawei and IBIS, beginning with the first IBIS Summit in China, held in Shanghai in 2005. He described that he and Huawei were very pleased that IBIS could once again hold an international event in China and was confident of its success. Michael Mirmak made a few brief comments regarding the history and growth in IBIS, and asked for the help and continued support of Chinese companies and engineers in advancing IBIS standard development. He concluded by thanking the primary sponsor Huawei, plus the co-sponsors, Cadence, Mentor Graphics, SiSoft, Sigrity and Synopsys for their financial and logistical support. Jing Lin, Deputy Division Chief of the Shanghai Municipal Informatization Commission, Information Industry Administration Division provided a few comments regarding IBIS, global standards and China. She noted that sustainable development, globalization and the rise of knowledge-based societies are the driving forces both of world and IT technology. She added that the Chinese government is promoting technology for national development, rising to meet the level of other leading countries. Doing this includes getting involved in international standards. The success of events such as the IBIS Summits would mean that "Chinese companies have arrived." The regular presentations followed the conclusion of the introductory remarks. THE DIRECTION OF IBIS AS A STANDARD Michael Mirmak, Intel Corporation (USA) Michael began the formal agenda of presentations by summarizing the state of IBIS today and its history since version 2.1. He noted the steady growth of the specification in features, including the addition of support for the EBD format, Berkeley SPICE, the Verilog-AMS and VHDL-AMS languages and the proposed introduction of links to ICM and user- defined measurements. He briefly outlined the recent proposal to add an application programming interface (API) to IBIS, to support additional languages such as C, for advanced channel analysis. He concluded by calling upon the participants to register their opinions on the API through the IBIS Open Forum. Sudarshan Honnudike asked whether IBIS includes leakage information. Michael Mirmak responded that it can, in the I-V tables. IBIS MODEL VALIDATION REPORT Qi Zheng, Fiberhome Telecommunications Technology (China) Qi reviewed two IBIS models, comparing validation results in simulation for them against transistor-level SPICE models of the same devices. The comparisons omitted package effects, and included various test fixtures and V-T table variations. The first model showed fairly good correlation to the SPICE model when 1 rising and 1 falling waveform were used for the V-T table data. However, the addition of 2 additional tables and more points in the tables significantly improved the results and avoided degradation seen in the edge rates of the two-table model. A second model showed excellent correlation with no changes needed. Qi concluded by noting that downloaded models need careful checking, and that package effects, particularly for power pins, need close scrutiny. Sudarshan Honnudike asked whether IBIS has a standard algorithm or recommended means of processing IBIS data tables. A discussion followed, concluding that the specification only defines the data format. The processing of the data is up to individual tools, though these tend to be similar. IBIS MODEL ENGINEERING FOR SI ANALYSIS Kazuhiko Kusunoki, Cybernet Systems (Japan) Kazuhiko began his presentation by noting that the number of users and usability of IBIS have been steadily growing over recent years. However, inefficient simulation procedures cost valuable time: rather than finding and correcting errors in IBIS after system simulations are complete, "front-loaded IBIS engineering" should rely on correcting errors in an IBIS early in the design process. These errors would include irregular data points, non-convergence issues in the V-T tables and clamp double-counting. He noted that this change in engineering emphasis would help prevent cases where relatively inexperienced engineers improperly use poor model data in simulation. He concluded by stating that such changes in approach would "help IBIS be more comfortable" for users and model makers. Lance Wang inquired whether the test utilities cited by Kazuhiko can be used to tune rise times based upon SPICE data. Kazuhiko responded that it can. CASE STUDY - SPICE MACROMODELING FOR PCI EXPRESS USING IBIS 4.2 Lance Wang, Cadence Design Systems Lance began by observing that the environment of PCI Express* in systems is particularly complex, with ISI effects being overcome through transmit equalization, or de-emphasis. In the particular example shown, de-emphasis was controlled through a 4-bit wide register, with voltage swing also having 4 bits of granularity plus high and low drive control. A SPICE macromodel using IBIS data was shown, where common and differential data was extracted for a differential buffer (in two stages) according to the IBIS 4.0 Cookbook. Additional IBIS structures were added to account for series pin-to-pin currents, while SPICE macromodeling code was used for the control inputs and the connections of the IBIS portions. Additional structures were added to improve correlation; these include an additional [Series Current] and Miller capacitances plus AC terminators. A comparison with a SPICE transistor-level model showed significant speed improvement where macromodeling was used. Lance concluded by recommending, in part, that IBIS should be opened to other commercial SPICE simulators under the multi-lingual extensions and that parameter passing should be enabled. SYSTEM-LEVEL TIMING CLOSURE USING IBIS MODELS Barry Katz, Signal Integrity Software (SiSoft) Barry provided an overview of the method used for analysis of timing at the system level. In particular, he focused on creating timing budgets using both knowledge of the system architecture (for the components and protocol) and derivations of timing equations before performing actual simulation. Design goals, interconnects and driver/receiver requirements all play a role. Signal integrity analysis permits the determination of the deviation between the ideal and realistic cases, including more effects. Further, an "executable" structured timing model can be used for both pre-route and post-route analysis. Barry concluded with an extended example using DDR2, where models, specifications and slew rate derating were combined to create detailed receiver eye diagrams. STATISTICAL EYE SIMULATION REQUIREMENTS ChunXing Huang, Huawei Technologies (China) ChunXing presented a detailed introduction to statistics-based simulations and procedures for generating eye diagrams. He noted that these methods, including convolution, were used to construct the eye as a post-processing technique, and could include complex design features (such as decision feedback equalization) and should also include jitter. He showed several types of algorithms for equalization, presented the equations for jitter and recommended the use of S-parameters for interconnect modeling. Bit error rates were estimated through the use of "bathtub" curves, and the entire method was demonstrated using a 10 Gbps system with both driver de-emphasis and receiver DFE. Crosstalk was included. Several bit patterns are used to generate the time-domain response used for analysis but the bit pattern itself may depend on the number of channels being analyzed together. Michael Mirmak asked about the kind of driver used in the examples. Was it a realistic design? Huang noted that a linear voltage source was used as the driver in all cases. METHODOLOGIES FOR MULTI-GIGABIT INTERCONNECT DESIGN Andrew Byers and Lawrence Williams, Ansoft (USA) Andrew presented with simultaneous translation by Steele Deng. He began by noting that extremely high-speed interfaces are rapidly replacing familiar older ones, demanding new signal and power integrity analysis techniques. His recommendations for the new approach were to collect comprehensive interconnect data from extraction and perform simulations in both the time and frequency domains. In particular, S-parameter data from 3D extraction was preferred for modeling interconnects, with TDR, VNA and eye diagrams all recommended for system analysis, including power plane analysis. Power distribution should also be carefully modeled, with a "challenge" issued to model producers: ensure that the IBIS models and tools you use result in accurate dI/dt information. As part of his conclusion, Andrew recommended the inclusion of S-parameters in IBIS. SYSTEM-LEVEL SSO SIMULATION TECHNIQUES WITH VARIOUS IBIS PACKAGE MODELS Sam Chitwood, Jack W.C. Lin* and Raymond Chen, Sigrity (USA and *China) Jack showed the basic response of systems to simultaneously switching outputs (SSN). Total SSN is a combination of system, package and power delivery effects. Driver effects can be included through good models and appropriate switching patterns; IBIS models should include both [Pin Mapping] and split C_comp data. Of the several traditional IBIS methods for modeling package parasitics, per-pin and global lumped RLC were deemed inappropriate, due to the lack of coupling. The [Package Model] keyword can be used to include coupling, which can be made accurate using optimization. An extended set of DDR2 comparisons were shown, where 16 bits were toggled under various conditions. Jack concluded by suggesting that IBIS package information was good for "what-if" analysis, but that S-parameters were recommended for "highly accurate SSO sign-off." Andrew Byers asked whether on-die decoupling was considered in the results shown. Jack responded that they were not, but this could be considered. USING S-PARAMETERS FOR BEHAVIORAL INTERCONNECT MODELING ShunLin Zhu, ZTE Corporation (China) ShunLin began by noting that wide-bandwith models are required for analysis of high-speed digital designs, and that S-parameters satisfy the major requirements for such models today: they can be easily generated, used and correlated, and can be applied to both transmission lines and vias. He showed several test extractions and correlations of S-parameter data, with excellent results. He also compared S-parameter models with RLGC models for the same circuit, and also with lab measurements. He continued by noting that the IBIS Interconnect Modeling (ICM) specification supports S-parameters, and that these would be desirable for IBIS packages. He reviewed a proposal for supporting ICM under the [External Circuit] keyword and showed how S-parameters might be applied to package modeling problems using a commercial simulation tool. Michael Mirmak added a few comments on ICM-to-IBIS links, noting that support for this feature has not yet been added to the IBIS specification due to the difficulty of supporting both multi-lingual and "traditional" IBIS buffers with ICM buffer models while avoiding major changes to the existing IBIS specification. JEITA EDA-WG ACTIVITY AND STUDY OF INTERCONNECT MODEL PART-3 Takeshi Watanabe, NEC Electronics and Hiroaki Ikeda, Japan Aviation Electronics (Japan) Takeshi provided an overview of JEITA (Japan Electronics and Information Technology Industries Association) activities related to IBIS and EDA. JEITA's membership has interests in SI, EMI and PI (power integrity) in component types including ICs, RF modules, passive components, packages, oscillators, connectors, cables, PCBs and flexible PCBs. JEITA's major short-term interests include studies of interconnect models, creating models of passive components and interconnects, plus creating an open IBIS-related modeling website. Hiroaki presented the details of numerous experiments using measurement and simulation data. Eye diagram, vector network analyzer (for S-parameters) and TDR data was collected for comparison against four vendor's simulation tools. Test boards included differential pairs, vias, filters, a plane split and a connector, each tested separately. Simulation tool responses varied widely, with some showing excellent model-to-measurement correlation, with others showing considerable deviation. Further experiments are in progress. Michael Mirmak asked whether the models and analysis data sets were collected using ideal or non-ideal return paths. Ikeda responded that all data sets were taken using ideal return paths. IBIS 4.2 and VHDL-AMS FOR SERDES AND DDR2 ANALYSIS Ian Dodd and Gary Pratt, Mentor Graphics (USA) Ian's presentation was simultaneously translated by MingGang (Simon) Hou Ian began by noting that traditional IBIS lacks features needed by modern buffer designs, such as pre-compensation and data recovery. He also noted that specialized measurements for these features do not exist in traditional IBIS either, but are now supported through the multi-lingual extensions. He compared SPICE and VHDL-AMS and Verilog-AMS as multi-lingual alternatives, stating that, while SPICE was popular, the *-AMS languages offer standardization and speed of simulation as advantages. Mixing the approaches may be a viable alternative. In two examples, Ian showed that VHDL-AMS could be used to model a serial differential transmitter, simulating up to 10 million bits overnight. He also showed that IBIS 3.2 models could be combined with additional VHDL-AMS code to provide sophisticated measurements for interfaces such as DDR2. In both examples, he emphasized that both the *-AMS and SPICE macromodeling approaches in the industry today are viable, and that a combination of SPICE with IBIS 3.2-style models would be desirable to support under the IBIS specification. IBIS MODELING OF DDR2 IN CONJUNCTION WITH LINEAR CHANNEL ANALYSIS Ian Dodd, Mentor Graphics Ian presented a brief summary of on-going work with DDR2 and linear channel analysis. He noted that time-domain signal integrity simulation tools sometimes encounter difficulties with predicting resonances, as these resonances are dependent on certain bit sequences (due to ISI). Linear channel analysis may predict these resonances, but drivers such as those used for DDR2 may be non-linear (for example, when overshoot is concerned). Ian showed a DDR2 system simulation using IBIS 4.2 drivers, where linear channel analysis is used to determine a worst-case bit sequence. Eye diagrams are compared between linearized drivers and a full non-linear representation. A 6% non-linearity is predicted in the full driver design, based upon multi-bit simulations. The resulting eye diagrams were highly similar. The system differs from other linear analyses in that it is "multi-drop" rather than serial-differential. One questioner inquired about the estimation of 6% non-linearity. Ian explained that the value was the deviation between the response of single pulses (high and low) versus a pole-zero analysis (similar to an S-parameter extraction). He also noted that the driver was the most likely culprit in the non-linearity of the system, as the connector models were examined and found to be very ideal. Michael Mirmak asked whether the system being tested was truly "non-linear" or "non-time-invariant." In other words, if the system analysis technique assumes LTI (linear and time invariant) response, could the driver in fact be linear but time-varying? Additional questions were asked regarding the number of bits used. Ian responded that 1 million (10^6) bits were simulated. He also noted that the bit pattern convolution simulations assumed a Gaussian pulse response. ODT, PRE-EMPHASIS AND SPEED Bob Ross, Teraspeed Consulting Group Bob presented an overview of three issues affecting advanced IBIS models. He summarized his recommended approach to properly modeling on-die terminators as to "model the device structure." This means that mimicking the actual structure of an on-die terminator will usually prove most effective in properly representing its behaviors through IBIS I-V clamp tables, particularly when using his "Deviate, Extrapolate, Calculate" process. Bob also noted, through several examples, how a structural approach can be used to model pre-emphasis through the [Driver Schedule] keyword. He concluded by noting, through an extreme example, that no actual limit exists on the transition speed of the device modeled under traditional IBIS. CONCLUDING ITEMS Michael Mirmak concluded the discussions by again thanking the co-sponsors, presenters and participants for the success of the Summit. He adjourned the meeting around 5:20 PM. NEXT MEETING The next IBIS meeting is the Asian IBIS Summit (Japan) and will be held October 31, 2006 at JEITA headquarters in Tokyo, Japan. The next IBIS Open Forum teleconference will be held November 17, 2006 from 8:00 AM to 10:00 AM US Pacific Time. ============================================================================ NOTES IBIS CHAIR: Michael Mirmak (916) 356-4261, Fax: (916) 377-3788 michael.mirmak@intel.com Server Platform Technical Marketing Engineer, Intel Corporation FM5-79 1900 Prairie City Rd. Folsom, CA 95630 VICE CHAIR: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 SECRETARY: Randy Wolff (208) 363-1764, Fax: (208) 368-3475 rrwolff@micron.com Simulation Engineer, Micron Technology, Inc. 8000 S. Federal Way Mail Stop: 01-711 Boise, ID 83707-0006 LIBRARIAN: Lance Wang (978) 262-6685, Fax: (978) 262-6363 lwang@cadence.com Senior Member, Technical Staff, Cadence Design Systems, Inc. 270 Billerica Road Chelmsford, MA 01824 WEBMASTER: Syed Huq (408) 525-3399, Fax: (408) 526-5504 shuq@cisco.com Manager, Hardware Engineering, Cisco Systems 170 West Tasman Drive San Jose, CA 95134-1706 POSTMASTER: Bob Ross (503) 246-8048, Fax : (503) 239-4400 bob@teraspeed.com Staff Scientist, Teraspeed Consulting Group 10238 SW Lancaster Road Portland, OR 97219 This meeting was conducted in accordance with the GEIA Legal Guides and GEIA Manual of Organization and Procedure. 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