CONTENT OF THE ASIAN IBIS OPEN FORUM SUMMIT MEETING October 31, 2006 Tokyo, Japan .zip Compressed .ppt, .pps Power Point .doc Word .ps Postscript .pdf Acrobat .txt Text .jpg Pictures ADMINISTRATIVE DOCUMENTS: 00readme.txt This Document a103106.txt Agenda m103106.txt Minutes m120806.txt Minutes with corrected attendence numbers PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION): watanabe.zip JEITA EDA - WG Activity (.ppt) watanabe.pdf Takeshi Watanabe and JEITA (NEC Electronics, Japan) mirmak.zip The Direction of IBIS as a Standard (.ppt) mirmak.pdf Michael Mirmak (Intel Corporation, USA) katz.pdf System-Level Timing Closure Using IBIS Models Katz, Barry, (Signal Integrity Software (SiSoft), USA) dodd.zip IBIS 4.2 and VHDL-AMS for Serdes and DDR2 Analysis (.ppt dodd.pdf with some notes) Ian Dodd, Ian and Gary Pratt (Mentor Graphics Corporation, USA) Presented by Minoru Ishikawa (Mentor Graphics, Japan) muranyi.pdf PDA for SI Analysis in LTI Systems - A VHDL-AMS Test Case Arpad Muranyi and Michael Mirmak (Intel Corporation, USA) Presented by Michael Mirmak (Intel Corporation, USA) ross.zip ODT, Pre-Emphasis, and Speed (.ppt) ross.pdf Bob Ross (Teraspeed Consulting Group, USA) wang.pdf Case Study: Spice Macromodeling for PCI Express Using IBIS 4.2 Lance Wang (Cadence Design Systems, USA) ikeda.zip Study of Interconnect Model (.ppt) ikeda.pdf Hiroake Ikeda and JEITA Japan Aviation Electronics, Japan) chitwood.pdf System-Level SSO Simulation Techniques with Various IBIS Package Models Sam Chitwood*, Jack W.C. Lin**, and Raymond Y. Chen* (Sigrity, *USA and **China) Presented by Yutaka Honda (ATE Service Corporation (Sigrity), Japan kusonoki.zip IBIS Model Engineering for SI Analysis (.ppt) kusonoki.pdf Kusunoki, Kazuhiko (Cybernet Systems, Japan)