CONTENT OF THE DESIGNCON EAST IBIS OPEN FORUM SUMMIT MEETING
September 19, 2005
Worcester, Massachusetts

   .zip  Compressed
   .ppt, .pps  Power Point
   .doc  Word
   .ps   Postscript
   .pdf  Acrobat
   .txt  Text

ADMINISTRATIVE DOCUMENTS:

00readme.txt     This Document
a091905.txt      Agenda
m091905.txt      Minutes

PRESENTATIONS AND ACTUAL TITLES (IN ACTUAL ORDER OF PRESENTATION):

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mirmak1.zip      IBIS Chair's Report and Roadmap (.ppt)
mirmak1.pdf      Michael Mirmak, Intel Corporation

ross1.zip        Version 3.2 Experience Modeling Fast, Two-Tap
ross1.pdf        Pre-emphasis Buffer (.ppt)
                 Bob Ross, Teraspeed Consulting Group

westerhoff.zip   An IBIS 4.1 Macro Library for Simulator Independent
westerhoff.pdf   Modeling (.ppt)
                 Arpad Muranyi, Intel Corporation; and
                 Todd Westerhoff and Mike LaBonte, Cisco Systems
                 Presented by Todd Westerhoff, Cisco Systems

ross2.zip        Extracting On-Die Terminators (.ppt)
ross2.pdf        Bob Ross, Teraspeed Consulting Group

haller1.zip      IBIS Parser BUG90 Ad-Hoc Presentation (.ppt)
haller1.pdf      Bob Haller, Signal Integrity Software (SiSoft)

haller2.zip      IBIS "Over Clocking" Case (.ppt)
haller2.pdf      Bob Haller and Eric Brock, Signal Integrity Software
                 (SiSoft)
                 Presented by Bob Haller, SiSoft

ross3.zip        Asian IBIS Summit Update (.ppt)
ross3.pdf        Bob Ross, Teraspeed Consulting Group