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                      AGENDA, EDI CON IBIS SUMMIT            
                     Wednesday, September 13, 2017

                       Hynes Convention Center 
                           900 Boylston St 
                           Boston, MA 02115 
                                    
                              Room: 104

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12:00  FREE LUNCH

13:00  SIGN IN

13:10  WELCOME AND INTRODUCTIONS
         Mike LaBonte (Signal Integrity Software (SiSoft))

13:15  IBIS Update
         Mike LaBonte (Signal Integrity Software (SiSoft))

13:30  Leveraging IBIS Capabilities for Multi-Gigibit Interfaces
         Ken Willis (Cadence Design Systems)

14:30  BREAK, REFRESHMENTS (30 Minutes)

14:00  Addressing DDR5 Design Challenges with IBIS-AMI
       Modeling Techniques
         Todd Westerhoff, Doug Burns, Eric Brock
         (Signal Integrity Software, (SiSoft))
         [Presented by Todd Westerhoff,
         (Signal Integrity Software, (SiSoft))]

14:45  BREAK, REFRESHMENTS (30 Minutes)

15:15  Interconnect Modeling Using IBIS-ISS and Touchstone
         Michael Mirmak (Intel Corporation)
         [Presented by Mike LaBonte
         (Signal Integrity Software (SiSoft))]

15:45  IBIS-AMI Dual Models: Why the Jitters?
         Mike LaBonte (Signal Integrity Software (SiSoft))

16:30  OPEN DISCUSSION

16:50  CLOSING REMARKS
         Mike LaBonte (Signal Integrity Software (SiSoft))

17:00  END OF MEETING

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REGISTRATION INFORMATION

People involved in IBIS Model development, EDA tool development,
and digital circuit design are invited to participate to the
Summit meeting. If you plan to participate, please register with
the information below:

   Name:
   E-mail address:
   Company:

Send to:

   Lance Wang (lwang@iometh.com)

SPONSORS:

   Signal Integrity Software (SiSoft)
   Teraspeed Labs

EDI CON CONFERENCE INFORMATION AND TRAVEL DIRECTIONS

   See http://www.ediconusa.com/venue.asp for travel directions,
   IBIS meeting hotel and other information.

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