RE: [IBIS-Users] IBIS and HSPICE simulation result question


Subject: RE: [IBIS-Users] IBIS and HSPICE simulation result question
From: Jeremy Plunkett (jeremy@serverworks.com)
Date: Tue Mar 26 2002 - 13:49:59 PST


hi,
not sure if I should address you by Huo or Gang...let me know?

sorry for the misunderstanding, if your model is both the source and
reciever then your input clamps are the determining factor. I am surprised
that the IBIS model would should higher over/undershoot than the spice
model; typically if there is any error it is double-counting the clamp
current(clamps end up 2x as strong as the spice deck), not undercounting it.

When you are testing the model, do you have the hspice B element set up with
power=on or power=off? It might be worth your while to try both settings
and compare the results. Also, make sure that you have all necessary and
optional nodes and voltages defined for the model type you are using. Don't
leave out the supply connections for the power clamp and ground clamp, not
all hspice versions include them as a default, no matter what the manual may
say.

Also, check that the buffer capacitance is the same between the ibis model
and spice deck at the process and temperature you are using. Capacitance
can vary significantly between process corners and even as the pad voltage
varies from one supply rail to the other and especially beyond the rails;
the IBIS format is not flexible enough to represent this at the present
time. If the capacitance of the spice model in the conditions at the pad
when the overshoot occurs is significantly higher than the capacitance
specified in the IBIS model, then you will see higher overshoot in the IBIS
model even though the diode IV curves were extracted correctly.

Regarding the diode resistance, if you have the physical part in hand or
even just similar parts made in the same process, you can measure the diode
clamp resistance(for one case of process, and at room temperature) fairly
easily. Just connect the part to it's standard supplies (but preferably not
to any other valuable circuitry), and connect a variable voltage pulse
source to a tristated signal pin. Set the pulse source to drive the signal
pad beyond the rail with a duty cycle of not more than 10%, and measure the
current flowing into the part by measuring the voltage at the pin with an
oscilloscope. The pulse source has a 50ohm output, so the voltage you
measure at the pin will not be the voltage that you set up on the front
panel. Measure the peak of that voltage (it should be a square/rectangular
waveform), and calculate the clamp current as Ic=(2xVf-VL)/50 where Ic=clamp
current, Vf=pulse voltage set at the front panel, and VL=peak voltage
measured at the pin. Measure the clamp current for pin voltages of 1v and
2v past the rail, then calculate the clamp resistance as Rc=1/(I1-I2), where
I1 and I2 are the respective current readings.

regards,
Jeremy

|>--/\/\/--((((((((()--|>

Jeremy Plunkett
Signal Integrity Engineer
ServerWorks Corp
www.serverworks.com

|>--/\/\/--((((((((()--|>

-----Original Message-----
From: ghuo@lsil.com [mailto:ghuo@lsil.com]
Sent: Tuesday, March 26, 2002 12:11 PM
To: Jeremy Plunkett
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS and HSPICE simulation result question

Hi, All

Thank Jeremy for your response.

I should clear myself, the simulation with problem is a driver drive a
transmission then to the same I/O cell as the receiver. The simulation shows
good correlation when driving a open transmission line or a 50 Ohm load.

Well, I got a 'extreme currents present in GND clamp curve' warning when
running ibischk3 (around 30A). I know this is highly likely due to the
'perfect' diode with no intrinsic resistance in the HSPICE model per IBIS
cookbook. And the IBIS model may not correlate with the real buffer
performance, but I am surprised it did not correlate well with the HSPICE
model
simulation in this case, since the IBIS model is derived from the same
HSPICE
model I used.

Without further information on the diode information, is there a good way to
solve the problem? Will adding a small resistor with a fixed value (say 5-7
Ohm) do the trick?

Thanks in advance.
Huo,Gang

Jeremy Plunkett wrote:

> Gang,
> the IBIS model clamps will only affect the level of overshoot when the
model
> you created is the receiver. If you are driving the model output into a
> transmission line test load, the level of overshoot at the end of the line
> will depend on the edge rate and output impedance of your IBIS model, but
> not on the clamps.
>
> I do a correlation check into a test load that matches the termination
> conditions that the driver will see in use, and correlate the waveform at
> _the driver's own output pad_ before looking at anything else. If the
> driver will be used on a terminated bus like DDR or GTL, use a test load
> that is a resistor equal to the transmission line impedance, connected to
> the termination voltage level. If the driver will be driving from the
> middle of a terminated bus, divide the transmission line impedance by two
> since the driver actually drives 2 transmission lines in parallel. If the
> driver will be used on unterminated lines, than the load should be a
pullup
> or pulldown resistor equal to the nominal trace impedance.
>
> If your extraction was accurate, you should see near-perfect correlation
of
> the output waveform into these loads. In particular, if you do a
> correlation into the same loads that are used for the IBIS model VT curves
> (usually 50 ohms pullup and pulldown), and you don't see 99% perfect
> correlation, then there is definitely a problem with either the model or
> your simulation setup.
>
> Good luck, hope this helped!
>
> Jeremy
>
> |>--/\/\/--((((((((()--|>
>
> Jeremy Plunkett
> Signal Integrity Engineer
> ServerWorks Corp
> www.serverworks.com
>
> |>--/\/\/--((((((((()--|>
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf
Of
> Gang Huo
> Sent: Monday, March 25, 2002 12:47 PM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] IBIS and HSPICE simulation result question
>
> Hi All,
>
> When I try to correlate a IBIS I/O model simulation with HSPICE model
> using HSPICE version 2000.4, the result is pretty good on the standard
> load and open transmission line load. One thing concerns me is that in
> the simulation of a load of transmission line to receiver simulation,
> the overshoot level of the signal is much higher when using the IBIS
> model than the HSPICE model, (the difference between two case is 0.5V
> nominal and 0.7V in best case, this is a 3.3v I/O buffer).
>
> I doubt this may be because of the clamp tables in the IBIS model. But
> as the creator of the model, I am pretty confident that the clamp tables
> in the IBIS model are correct, so can someone give me an idea what else
> in the IBIS model may cause this? Will this cause a problem to the
> users? And is there any good way to address this issue when creating the
> models?
>
> Thanks in advance,
> Gang Huo
>
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