Subject: RE: [IBIS-Users] IBIS Imponderables
From: Jeremy Plunkett (jeremy@serverworks.com)
Date: Wed Apr 03 2002 - 00:31:40 PST
Hi Kim,
I have never been involved in the IBIS specification process, but I have built a lot of models, and here are my best-guess answers to your questions...
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Kim Helliwell
Sent: Tuesday, April 02, 2002 10:59 AM
To: 'ibis-users@eda.org'
Subject: [IBIS-Users] IBIS Imponderables
I'm sure I'm not the only person who has wondered
about these:
1. Why is a mismatch in the file name an error, rather than
a warning? In fact, why does it matter at all?
This was probably intended to prevent people from modifying the filename from the original (or make it more difficult, at least). This is because an IBIS file is similar to a specification (more detailed, but less official) and semiconductor vendors do not want modified versions of their IBIS models floating around. There should be one most current revision of an IBIS model for a given part, and if people are prevented from renaming the file then it is easier to confirm that they are all using the same file. Of course if model users want to work around this they can (and do), but they have to go through the hassle of changing the name in 2 places.
2. Why are only lowercase letters allowed in an IBIS file name?
As others mentioned, this helps ease transfer between operating systems.
3. Why are AC mismatches warnings rather than errors?
The mismatch that this indicates is between the initial or final voltage of a VT curve and the predicted (steady-state)operating point based on the intersection of the IV curve with the load line for the VT curve load resistance. There are 2 likely reasons why this mismatch occurs:
1) the model maker trimmed off too much of the initial portion of the VT curve data before the edge, and either cut off the very beginning of the transition or set the start point of the VT curve data in the middle of a "pre-shoot" hump in the data (bounce on the signal that occurs prior to switching due to capacitive coupling between the gate and source/drain terminals of the output transistors).
2) the model maker set the end of the VT curves at a point where the signal had not yet completely settled at one or more of the PVT corners. This is often unavoidable if the buffer will be used in a very fast switching environment, since some simulation programs (specifically Hspice, to my knowledge, and possibly others) will give erroneous waveforms if the VT curves are longer than the pulse width when the model is used in simulation. This requires that a buffer which will be used at a frequency of 200MHz (2.5ns pulse width) must have VT curves less than 2.5ns in duration, maybe 10-15% less if the duty cycle or frequency will be varied in simulations.
Neither of these situations has a large effect on the accuracy of the simulation results with any simulators I've used, since in the 1st case any errors in the waveform occur prior to the portion of the edge which crosses the receiver thresholds and in the 2nd case the waveform errors would occur while the output voltage is at a steady-state high or low. The sort of error that does occur depends on exactly what the simulator does in the face of the inconsistent VT data, but I am fairly sure that most if not all simulators either modify the curves with interpolated values or revert to some approximation of the IBIS 1.0 (no VT curves) algorithm at the discontinuities and just apply the VI curves to the load, which will result in a fairly smooth transition either way.
4. Why does s2ibis2 appear to generate IBIS models
with AC mismatches in the first place? (Judging
from the number of IBIS models I've seen that
used s2ibis2 and had such problems, it is
apparently the norm.)
The 2 situations above are very common, the 1st case happens more often with slow-speed logic and inexperienced model makers who determine the beginning of the transition in an arbitrary manner, the 2nd case is more common with very high speed logic and is often unavoidable.
Since avoiding the mismatch warning involves modifying the VT curves from the original data based on spice or measurement, whether to do so in a given case is a judgment call, and is probably not worth doing unless there is a significant chance that leaving the model with the mismatch will result in simulator errors.
Feel free to provide answers or add your own imponderables.
Kim Helliwell
Apple Computer
kimgh@apple.com
408 974 9936
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