RE: [IBIS-Users] The buffer have a outside terminal: Pls teach me modeling method


Subject: RE: [IBIS-Users] The buffer have a outside terminal: Pls teach me modeling method
From: Hegazy, Hazem (hazem_hegazy@mentorg.com)
Date: Mon Jun 10 2002 - 06:34:27 PDT


Hi,
From what I see here you made V-T table extraction with the PAD connected
with 50 Ohm resistor to ground and not VDD/2.
This clear from the ibischk3 warning it-self, as the wave form starts from
zero and going to 1.29 volts. This only happens when the load is connected
to ground or the starting (first) edge begins from wrong dc (Then you might
try the second rising/falling edge).

While the V_fixture inserted in the IBIS model was 1.5 volts for the same
V-T table!!
 
"ERROR - Model HSTL1: The [Rising Waveform]
      with [R_fixture]=50 Ohms and [V_fixture]=1.5V
      has TYP column DC endpoints of 0.00V and 1.29v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.16V and 1.50V),
      a difference of 100.00% and 14.00%, respectively."

I think the I-V data is right as it doesn't begin from 0.0V at 50 Ohm to
1.5V which is normal.

BR,

-----Original Message-----
From: Takanobu Ura [mailto:t-ura@pb.jp.nec.com]
Sent: Monday, June 10, 2002 2:02 PM
To: ibis-users@server.eda.org
Cc: ???????; Ura Takanobu
Subject: [IBIS-Users] The buffer have a outside terminal: Pls teach me
modeling method

Dear All,

Regarding IBIS modeling method, In case of the buffer have a outside pullup
terminal, Do we need to analyze with waveform-SPICE-netlist including
outside
pullup terminal?

For example, HSTL buffer is used as follows:
 Buffer terminal Transmission line
 -----><-------><--------
        Vdd/2 Vdd/2
         -+- -+-
          | |
          R R
          | R=50ohm |
     |>---+------/////-----------+---|>

We analyzed as follows:
V-I table

       |>--------------+
                       |
                       V External Voltage Sweep
                       |
                      /// GND

V-t table

   RisingWaveform/FalingWaveform
            VDD/2
             -+-
              |
              R1 V_fixture=Vdd/2
              | R_fixture=R1
   Vin-|>-----+

When we generate IBIS-model with above the SPICE-netlist, Ibischk3 reports
the below error message:
ERROR - Model HSTL1: The [Rising Waveform]
      with [R_fixture]=50 Ohms and [V_fixture]=1.5V
      has TYP column DC endpoints of 0.00V and 1.29v, but
      an equivalent load applied to the model's I-V tables yields
      different voltages ( 0.16V and 1.50V),
      a difference of 100.00% and 14.00%, respectively.

Please let me know modeling method which the buffer have a outside pullup
terminal.

Best regards,
T.Ura
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