RE: [IBIS-Users] Rising/Falling Waveform generation


Subject: RE: [IBIS-Users] Rising/Falling Waveform generation
From: Dagostino, Tom (tom_dagostino@mentorg.com)
Date: Mon Jul 01 2002 - 09:22:50 PDT


The "problem" you are seeing is in fact not and issue at all. All buffers have a finite output impedance. For a logic gate the output impedance will range from about an Ohm to well over 50 Ohms. The output impedance forms a voltage divided between the open circuit output voltage and the load (50 Ohms in this case). True, you gate will swing 0 to Vdd open circuit but it will not swing the same range with 1 Ohm or 10 Ohms or even a 50 Ohm load. Even Bonneville Dam has a finite output impedance.

Tom Dagostino
Modeling Manager
Mentor Graphics Corp.
SAS
tom_dagostino@mentor.com
503-685-1613

-----Original Message-----
From: John Phillippe [mailto:ra6314@email.sps.mot.com]
Sent: Friday, June 28, 2002 3:43 PM
To: Scott McMorrow
Cc: John Phillippe; ibis-users@server.eda.org
Subject: Re: [IBIS-Users] Rising/Falling Waveform generation

Scott McMorrow wrote:
>
> John,
>
> My guess is there is something wrong with your simulation deck setup.
> Rfixture and Vfixture is simple load placed on the output of your
> buffer during VT table extraction. It is no different than setting up
> your spice deck by hand, attaching a pulse source to the input of the
> buffer and a resistive load to the output of the buffer and simulating.
> If your buffer is capable of driving a 50 ohm load, then there should
> not be a problem with spice2ibis. If there is, it would be generally a
> setup or connectivity problem.
>
> An Rfixture of 100K would be useless to an ibis simulator, since the
> simulator will attempt to scale the rising and falling waveforms to the
> actual load impedance of 50 to 75 ohms in system. This scaling would
> cause significant waveform errors.
>
> My suggestion is to setup the buffer independently of spice2ibis and
> verify that it actually is capable of driving a standard load. If it
> is, then you have an issue with the connections in the decks used for
> ibis extraction.
>
> Regards,
>
> Scott
>
> John Phillippe wrote:
>
> >Dear Everyone,
> > I can't seem to generate decent rising and falling waveforms in IBIS.
> >After looking at the generated spice files, I found that the problem was
> >with the Rfixture and Vfixture. I found that if I didn't use a test
> >fixture of any kind, then the waveforms came out correct. However I had
> >to manually generate them. So I went back and tried monkeying with the
> >Rfixture values, and found that a 100K resistor seems to allow IBIS to
> >generate a good waveform.
> > I've never used an IBIS model in a simulation environment before, and
> >so I guess my question is regarding the Rfixture, and what it is used
> >for. Could I manually generate my edges and then specify an Rfixture of
> >0 ohms in the ibis file? Is having an Rfixture of 100k going to cause
> >any problems for the end users?

Scott,
  When I setup the rising/falling test with a 50ohm load, and let s2ibis
do it's runs, I get corresponding rising and falling waveforms, my
problems lie in the fact that my waveforms never go from gnd to Vdd.
The following 4 lines are taken from one of my .s2i files.

[Rising waveform] 50 5.0 4.75 5.25 NA 50pF 233.0m 9.35nH 0.87pF
[Falling waveform] 50 5.0 4.75 5.25 NA 50pF 233.0m 9.35nH 0.87pF
[Rising waveform] 50 0 NA NA NA 50pF 233.0m 9.35nH 0.87pF
[Falling waveform] 50 0 NA NA NA 50pF 233.0m 9.35nH 0.87pF

When looking at the results, the rising and falling waveforms with a
Vfixture of 5V, have a rising waveform starting at a value above 0V, and
ending at 5V. The falling waveform starts at 5V, and ends above 0V. The
waveforms with a Vfixture of 0V have a bottom of 0V, but a ceiling of
less than 5V. It doesn't "seem right." If this is how it should be
however, someone please let me know! I would expect voltage range of
between 0V and 5V. Thanks.

-- 
John Phillippe
SPS, 32 Bit Embedded Controller Division, IC Creation
Motorola      -  512-895-1835
Austin, TX    -  ra6314@email.sps.mot.com
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