Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question
From: rob.mataheroe@philips.com
Date: Thu Jul 25 2002 - 08:10:17 PDT
Hello All,
R Series appears to be not supported by the Ibis simulators, which is a shame, since it has been prepared so well in Ibis 3.2
What do you think about the following approach:
Use a resistor of Rdiff/2 to a fixed point at the level of the desired common mode voltage.
This could be achieved by using the model Terminator and using Rgnd and Rpower.
Looking forward to your reactions,
Rob
__________________________________________________________________________
Rob Mataheroe Philips Semiconductors bv
P.G. Logic Product Group PD&S Building AM1.108
Senior Design Modeling Engineer Gerstweg 2
Tel. ++31 (0)24 353 2370 6534 AE Nijmegen
Fax. ++31 (0)24 353 2820 The Netherlands
Email: Rob.Mataheroe@philips.com
Seri: matahero@nyhp04
"Hegazy, Hazem"
<hazem_hegazy@mentor To: "'Peter LaFlamme '" <plaflamm@amcc.com>
g.com> "'Hassan Ali '" <Hassan.Ali@fidus.ca>
Sent by: cc: "'ibis-users@server.eda.org '" <ibis-users@server.eda.org>
owner-ibis-users@ser (bcc: Rob Mataheroe/NYM/SC/PHILIPS)
ver.eda.org Subject: RE: [IBIS-Users] LVDS RECEIVER TERMINATION Question
Classification:
07/23/02 11:01 PM
Hi,
I've a solution...I didn't test it yet but, I suggest that based on an old solution of mine for 100 terminated LVDS DRIVERS in IBIS summit Jan 2001 "hegazy.pdf or zip on IBIS home page".
In the driver case, I consider the internal termination as a part of the buffer itself, I could not take it away "In some cases we can" so, I want to get the I-V characteristics based on this.
What are the I-V characteristics? Simply, it's the steady state solution of the voltage and current at all possible loads.
So, I put a resistor between P node and N node and measure "steady state voltage and current" now, vary the resistor value from zero to infinity (open circuit) and do the same extraction to complete your I-V table. You will have the actual behavior of the
buffer (Interactive) on all possible loading conditions. This is verified with a lot of LVDS buffers for very famous customer.
For the receiver we can't do that as there is no source of current like in the driver case to measure the I and V.
So, my suggestion is to put a voltage source between the p and n nodes (differential voltage source). Vary the voltage source value in normal DC analysis and measure the P voltage with the current through the voltage source to form the I-V table with the
interaction of the n node inherited inside it.
I'll try this solution with some validation and keep you all informed.
I might have goofed!!
BR,
-----Original Message-----
From: Peter LaFlamme
To: Hassan Ali
Cc: ibis-users@server.eda.org
Sent: 7/23/02 6:52 PM
Subject: Re: [IBIS-Users] LVDS RECEIVER TERMINATION Question
Hi Hassan,
Thanks alot for the comments and information. I have done the same thing
previously in simulations. I have also received input models that had
the internal termination modeled as a dynamic clamp. In comparisons
between dynamic clamp modeled terminations
and your method, I found that (just in my case) there was not real good
correlation.
Regards,
Peter
Peter LaFlamme
Applied Micro Circuits Corp.
System Applications Engineer
200 Minuteman Rd, 3rd Floor
Andover, MA 01810
978-247-8470 phone
978-623-0055 Fax
Hassan Ali wrote:
>
> Hi Peter,
>
> I had the same situation a few months ago and I only had to go with an
> adhoc solution.
>
> Yes indeed most simulators do not have good support for differential
> models with [R Series] termination. I ended up creating a single-ended
> input buffer model (same for the P and N side) with no termination
> between P and N sides. This only captured the clamping function.
>
> In my simulation I had to recreate the terminated differential input
> buffer by using two single-ended buffers (one for the P and one for
the
> N pin) with a termination resistor tied between them. The package
> parasitics were also tied to the two pins. I manually changed the
values
> of the termination resistor and package parasitics to cover their
> variation in the typical, minimum and maximum corners.
>
> Probably there is a better solution, but that's what I did as a
> quick-and-dirty work-around.
>
> Regards.
>
> Hassan.
>
> Hassan Ali, Ph.D.
> Signal Integrity Specialist -Talented, innovative designers
> Fidus Systems Inc. -Highly competitive rates
> Tel: (613) 828-0063 Ext.342 -Fixed-price business model
> Fax: (613) 828-3113 -State-of-the-art design tools
> http://www.fidus.ca -Customer-friendly attitude
>
> -----Original Message-----
> From: Peter LaFlamme [mailto:plaflamm@amcc.com]
> Sent: Tuesday, July 23, 2002 9:01 AM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] LVDS RECEIVER TERMINATION Question
>
> Hi All,
> I am tasked with creating an IBIS model for an LVDS receiver cell that
> has an internal 100 ohm termination between the P and N nodes. I had
> asked Bob Ross about this a while ago and as usual he was very
helpful.
> >From his response I used the following
> implementation:
>
> |****************************************************************
> | Component: LVDSRCV
> |****************************************************************
> |
> [Component] LVDSRCV
> [Manufacturer] AMCC
> |
> |
> |
> [Package]
> | variable typ min max
> R_pkg 1E-3 NA NA
> L_pkg 1E-9 NA NA
> C_pkg 1E-12 NA NA
> |
> [Pin] signal_name model_name R_pin L_pin C_pin
> 1 PAD lvdsrcv NA NA NA
> 2 PADN lvdsrcv NA NA NA
> |
> [Series Pin Mapping] pin_2 model_name function_table_group
> 1 2 rterm_100
>
> |
> [Diff_pin] inv_pin vdiff tdelay_typ tdelay_min
> tdelay_max
> |
> 1 2 0.2 0 0
0
>
> [Model] rterm_100
> C_comp 0.1pF 0.1pF 0.1pF
>
> Model_type Series
> |variable R(typ) R(min) R(max)
> [R Series] 100 80 120
>
> [Temperature Range] 25.00 125.00 0.00
> [Voltage Range] 1.800 1.650 1.950
>
>
************************************************************************
> ****************
>
> I was able to get the model past the IBIS checker but my simulations
did
> not show the 100 ohm terminator. I was using a tool which I believe
does
> not support this implementation (no need to mention names). I have
seen
> other implementations where I believe
>
> a "Dynamic clamp" is used to model the termination behavior, but I am
> unsure. Can anyone guide me to some reference material or weigh in
with
> your experience or help.
>
> Thanks alot,
> Peter
>
>
>
> --
> Peter LaFlamme
>
> Applied Micro Circuits Corp.
> System Applications Engineer
> 200 Minuteman Rd, 3rd Floor
> Andover, MA 01810
>
> 978-247-8470 phone
> 978-623-0055 Fax
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