Re: [IBIS-Users] IBIS bump question


Subject: Re: [IBIS-Users] IBIS bump question
From: Fred Balistreri (fred@apsimtech.com)
Date: Fri Nov 22 2002 - 14:29:48 PST


It does not matter, so long as it does not get double counted. I believe
the solder bump may appear in the CAD package data base. If so it should
be made part of the package not the IC.

Best Regards,

Tom Dagostino wrote:
>
> I started to say the bump C should be part of the package but in reflection
> it seems to be part of the die. I'd vote for as part of C_comp because it
> is part of the metalization on the die.
>
> Tom Dagostino
> Device Modeling Division
> Teraspeed Consulting Group LLC
> 2926 SE Yamhill St.
> Portland, OR 97214
> (503) 430-1065
> tom@teraspeed.com
> http://www.teraspeed.com
>
> -----Original Message-----
> From: owner-ibis-users@server.eda.org
> [mailto:owner-ibis-users@server.eda.org]On Behalf Of Eric Hsu
> Sent: Friday, November 22, 2002 12:20 PM
> To: ibis-users@server.eda.org
> Subject: [IBIS-Users] IBIS bump question
>
> Hi all,
>
> For a wire-bond package, the RLC of the bondwire is generally considered
> to be part of the package. For a flip-chip package, is there a convention
> for how the bump parasitics should be handled? Is the bump to be
> considered part of the package, or part of the die(C_comp)?
>
> Regards,
>
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-- 
Fred Balistreri
fred@apsimtech.com

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