Subject: RE: [IBIS-Users] Modeling input receivers with on-die termination
From: herbert_lage@agilent.com
Date: Fri May 09 2003 - 09:59:40 PDT
Hi Todd, All,
This is a very interesting dicussion. I have to admit that since I started IBIS modelling a few years ago I occasionally spent more time constructing input buffers than output buffers, even though the former only require 2 tables.... Below are my thoughts based on my limited understanding of the IBIS standard:
Your proposal 1 is the simplest and should work with most simulators in my experience. I would use it when I have no information whatsoever about the internal structure of the buffer. A possible downside is that simulations in HSpice with the "power=off" option will become inaccurate since voltage fluctuations of the externally attached voltage source do not affect the buffer due to the missing Power clamp data.
Proposal 2 is my favourite approach, although I tend to use a modified version of it:
- Find the zero-current (say at a voltage Vterm) and the slope Rterm (at Vterm).
- Subtract the current (V-Vterm)/Rterm from the V-I data
- If the resultant curve is still monotonous, I proceed as decribed below, if not I would most likely use proposal 2 without any modification
- Therefore, IF the resultant V-I curve is monotonous, I split it into Power and Gnd Clamp (the current in the operating region is now ideally very small after the on-die termination has been subtracted)
- I then work out the resistances R1 and R2 of the voltage divider that produces the right on-die termination characteristic:
--- Power (VDDQ)
|
R1
|
--------- input pad
|
R2
|
------
---
-
with Vterm = VDDQ*R2/(R1+R2) and Rterm = R1*R2/(R1+R2)
- V-I data for R1 (connected to Power) is now added to the Power Clamp
- and V-I data for R2 (connected to Gnd) is added to the Gnd Clamp data
This modified approach should hopefully reflect the internal buffer structure fairly accurately. It looks complex, however, it can be implemented in a spreadsheet relatively easily. I usually extrapolate all data so that the whole voltage range between -VDDQ and 2*VDDQ is covered. I do not like to leave that to the simulation tools.....
Some months ago we actually discussed a 3rd approach. We wanted to create a clock-input buffer that had a voltage divider for biasing the input stage. We thought that we should be able to recreate the on-die circuit using the [Series Pin Mapping] keyword for mapping series resistors to Power and Gnd pins. However, in order to define the rail voltages for the Power pins, we also needed the [Pin Mapping] keyword to define Power and Gnd buses. The relevant parts of the model are attached below, it parses without errors. However, I am not so sure how this would behave in many IBIS simulators. A disadvantage is of course that with this approach you cannot tell the buffers characteristics from the V-I data.
If I am completely on the wrong track here please let me know.....
Best Regards,
Herbert.
|************************************************************
|
[IBIS Ver] 3.2
[File name] ref_clk.ibs
[File Rev] v1.0
[Date] October 2002
[Source] File originated at Agilent Technologies, Inc.
[Notes]
[Disclaimer] The usual....
|
[Copyright] Agilent Technologies, Inc. Copyright 2002.
[Component] HDMP-XXXX
[Manufacturer] Agilent Technologies, Inc.
|
[Package]
| variable typ min max
R_pkg 0.00ohms NA NA
L_pkg 0.00nH NA NA
C_pkg 0.00pF NA NA
|
[Pin] signal_name model_name R_pin L_pin C_pin
|
| Ref_clk receiver ports
APow REFCLK_pwr POWER
AGnd REFCLK_gnd GND
V25 REFCLK_P PAD_REFCKIN
V26 REFCLK_N PAD_REFCKIN
|
|
[Pin Mapping] pulldown_ref pullup_ref gnd_clamp_ref power_clamp_ref
|
APow NC RXPowBus1
AGnd RXGndBus1 NC
V25 NC NC RXGndBus1 RXPowBus1
V26 NC NC RXGndBus1 RXPowBus1
|
|
[Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max
|
| Input pins
V25 V26 275m NA NA NA
|
|
[Series Pin Mapping] pin_2 model_name
|
| DC-Biasing for Clock Inputs
V25 APow R_AVDD_3k6
V25 AGnd R_Gnd_4k2
|
V26 APow R_AVDD_3k6
V26 AGnd R_Gnd_4k2
|
|
|************************************************************
| DC-Biasing Clock Input Resistors
|************************************************************
|
[Model] R_AVDD_3k6
Model_type Series
|
| typ min max
C_comp 0.00p 0.00p 0.00p
|
[Voltage Range] 1.80 1.62 1.98
|
| variable R(typ) R(min) R(max)
[R series] 3887 3174 4579
|
| End of R_AVDD_3k6
|
|************************************************************
|
[Model] R_Gnd_4k2
Model_type Series
|
| typ min max
C_comp 0.00p 0.00p 0.00p
|
[Voltage Range] 1.80 1.62 1.98
|
| variable R(typ) R(min) R(max)
[R series] 4241 3475 4987
|
| End of R_Gnd_4k2
|
|
|************************************************************
| Model PAD_REFCKIN
|************************************************************
|
[Model] PAD_REFCKIN
Model_type Input
| REF_CLK Differential Receiver Pad
|
Vinl=0.80V
Vinh=1.20V
|
| Vinl and Vinh are overridden by Vdiff
|
| typ min max
C_comp 1.08p NA NA
| C_comp: art-extracted value
|
|Condition (typ) (min) (max)
|Process nominal slow fast
[Temperature Range] 75 110 0
[Voltage Range] 1.80 1.62 1.98
|
|
[GND_clamp]
|
| voltage I(typ) I(min) I(max)
|
-2.00 -4.57e-01 -4.81e-01 -4.07e-01
-1.40 -2.17e-01 -2.34e-01 -1.78e-01
-1.10 -9.70e-02 -1.11e-01 -6.30e-02
-1.00 -5.50e-02 -7.00e-02 -2.60e-02
-0.90 -1.49e-02 -3.00e-02 -1.23e-03
-0.80 -1.10e-03 -3.34e-03 -1.00e-08
-0.70 -7.50e-09 -3.01e-04 -7.56e-09
-0.60 -6.89e-09 -6.05e-09 -6.35e-09
-0.50 -5.19e-09 -5.19e-09 -5.15e-09
-0.40 -4.58e-09 -4.54e-09 -4.53e-09
-0.30 -3.52e-09 -3.53e-09 -3.54e-09
-0.20 -2.57e-09 -2.54e-09 -2.54e-09
-0.10 -1.54e-09 -1.51e-09 -1.59e-09
0.00 -0.39e-09 0.31e-09 -0.32e-09
0.10 0.54e-09 0.57e-09 0.59e-09
0.20 1.55e-09 1.58e-09 1.57e-09
0.30 2.54e-09 2.52e-09 2.56e-09
0.40 3.54e-09 3.57e-09 3.54e-09
0.50 4.52e-09 4.52e-09 4.52e-09
0.60 5.50e-09 5.57e-09 5.59e-09
0.70 7.08e-09 7.03e-09 7.07e-09
0.80 8.05e-09 8.00e-09 8.04e-09
0.90 8.51e-09 8.52e-09 8.51e-09
1.00 1.01e-08 1.09e-08 1.02e-08
1.10 1.03e-08 1.10e-08 1.04e-08
1.20 1.15e-08 1.11e-08 1.11e-08
1.30 1.20e-08 1.28e-08 1.23e-08
1.40 1.35e-08 1.36e-08 1.39e-08
1.50 1.45e-08 1.44e-08 1.40e-08
1.60 1.55e-08 1.52e-08 1.52e-08
1.70 1.64e-08 1.64e-08 1.64e-08
1.80 1.75e-08 1.70e-08 1.76e-08
1.90 1.82e-08 1.86e-08 1.88e-08
2.00 1.93e-08 1.96e-08 1.90e-08
2.10 2.05e-08 2.08e-08 2.01e-08
2.20 2.12e-08 2.12e-08 2.12e-08
2.30 2.24e-08 2.26e-08 2.23e-08
2.40 2.38e-08 2.32e-08 2.37e-08
2.50 2.49e-08 2.41e-08 2.40e-08
2.60 2.56e-08 2.58e-08 2.50e-08
2.70 2.67e-08 2.68e-08 2.62e-08
2.80 2.71e-08 2.75e-08 2.70e-08
2.90 2.81e-08 2.85e-08 2.81e-08
3.00 2.94e-08 2.92e-08 2.94e-08
3.10 3.06e-08 3.03e-08 3.09e-08
3.20 3.13e-08 3.10e-08 3.19e-08
3.30 3.21e-08 3.20e-08 3.21e-08
3.40 3.35e-08 3.30e-08 3.30e-08
3.50 3.40e-08 3.45e-08 3.43e-08
3.60 3.55e-08 3.50e-08 3.51e-08
3.70 3.60e-08 3.65e-08 3.67e-08
3.80 3.75e-08 3.70e-08 3.75e-08
3.90 3.85e-08 3.80e-08 3.85e-08
4.00 3.90e-08 3.93e-08 3.90e-08
|
|
[POWER_clamp] | Note: Vtable = Vcc - Voutput
|
| voltage I(typ) I(min) I(max)
|
-2.00 3.25e-01 3.84e-01 1.83e-01
-1.90 2.33e-01 2.95e-01 7.66e-02
-1.80 1.39e-01 2.05e-01 1.39e-02
-1.70 4.95e-02 1.20e-01 4.34e-03
-1.60 1.25e-02 4.14e-02 2.50e-03
-1.50 4.01e-03 1.17e-02 1.82e-03
-1.40 1.83e-03 3.90e-03 1.30e-03
-1.30 1.06e-03 1.67e-03 8.17e-04
-1.20 6.34e-04 8.74e-04 3.93e-04
-1.10 3.21e-04 4.68e-04 1.24e-04
-1.00 1.21e-04 2.14e-04 5.07e-05
-0.90 5.07e-05 8.05e-05 2.97e-05
-0.80 2.96e-05 3.72e-05 1.42e-05
-0.70 1.69e-05 2.18e-05 3.22e-06
-0.60 6.98e-06 1.19e-05 1.76e-07
-0.50 1.34e-06 4.55e-06 1.48e-08
-0.40 1.22e-07 8.47e-07 7.04e-09
-0.30 2.55e-08 9.03e-08 5.30e-09
-0.20 3.53e-09 2.02e-08 3.57e-09
-0.10 1.82e-09 1.05e-08 1.84e-09
0.00 0.43e-09 -0.43e-09 -0.40e-09
0.10 -1.74e-09 -1.76e-09 -1.77e-09
0.20 -3.55e-09 -3.50e-09 -3.53e-09
0.30 -5.35e-09 -5.35e-09 -5.39e-09
0.40 -7.05e-09 -7.02e-09 -7.05e-09
0.50 -8.70e-09 -8.70e-09 -8.70e-09
1.00 -1.75e-08 -1.75e-08 -1.75e-08
1.50 -2.64e-08 -2.65e-08 -2.69e-08
2.00 -3.47e-08 -3.48e-08 -3.43e-08
2.50 -4.39e-08 -4.38e-08 -4.30e-08
3.00 -5.25e-08 -5.29e-08 -5.29e-08
3.50 -6.18e-08 -6.19e-08 -6.16e-08
4.00 -7.10e-08 -7.19e-08 -7.17e-08
|
| End of input model PAD_REFCKIN
|
[End]
-----Original Message-----
From: Todd Westerhoff [mailto:twesterh@cisco.com]
Sent: 08 May 2003 07:44
To: Ibis-Users (E-mail)
Subject: [IBIS-Users] Modeling input receivers with on-die termination
Hi all,
This one has been bugging us for a while ... the discussions that took place
last week gave us the opportunity to take another look at this problem and
its different components. I have two solutions to propose, and would
appreciate feedback from the group.
I apologize in advance for a lengthy email. There's no other way I know to
describe the different components of the problem and the way they interact.
To start - the problem is accurately modeling the effect of on-die input
termination, most typically pulling the signal to a value of VDDQ/2, which
would be common for HSTL and SSTL signalling. The resistors in question (at
least in our case) were not discrete components in the package - they were
truly on-die. Hence, the resistance varied with process and was non-linear
over the operating range. Thus, we needed a way to extract the actual input
characteristics using the HSpice model and create the correct model in IBIS.
Simple enough, we thought - then it got deep.
To ended up breaking the problem down into three pieces -
1) The IBIS Specification
2) The process of creating models
3) How IBIS simulators use the data in the IBIS models
1) The IBIS Specification
-------------------------
Please correct me if I'm wrong here, but I believe the IBIS Spec doesn't
list any "standard" for the voltage range over which the behavior of the
[GND Clamp] and [POWER Clamp] should be specified. I took it as a given
that [Pulldown] and [Pullup] curves would range from -VDDQ to 2*VDDQ, and,
until last week, I would have expected to see the same range for the power
and ground clamps. That turned out not to be the case.
I also suspect that the IBIS spec has no comment on just how the simulator
is supposed to combine the data in the two clamp curves, should the points
overlap. That turned out to be a big sticking point.
2) The process of creating models
---------------------------------
There are two classes of people who create IBIS models from HSpice
simulations:
a) The gurus, who understand IBIS, HSpice and software well enough to
develop their own tools for extracting and compiling IBIS model data, and
b) The rest of us, who use some version of s2ibis2. Usually, it's one we've
compiled ourselves, with some collection of fixes implemented for problems
we have found on our own. I'm going to aim my comments squarely at s2ibis2,
with the assumption that's what most of the IBIS-modelmakers are basing
their efforts on.
When s2ibis2 was created, the developer noticed an interesting problem -
there is really no good way to separate the ground clamp curve from the
power clamp curve. With the [Pullup] and [Pulldown] curves, you can isolate
the behavior of transistor from the other by virtue of the output state.
However, if you model the input buffer and sweep the voltage from -VDDQ to
2*VDDQ, there's really no good way to separate the one clamp curve from the
other.
(When I talk about voltage from this point on, I'm going to use ground as a
reference, unless I specifically state that I'm using a power-based voltage
reference "a la IBIS". I'm also going to assume the ground clamp is active
between -VDDQ and 0V, the "operating region" for the device is between 0V
and VDDQ, and the power clamp is active between VDDQ and 2*VDDQ).
Of course, if you've got a normal input (without termination), the input
current is zero (or essentially so) throughout the operating region, so
there isn't really any problem. It doesn't much matter where the ground
clamp curve leaves off and the power clamp curve kicks in, because the
currents at those points are always zero.
However, the presence of on-die termination to VDDQ/2 presents an
interesting problem. The "zero current" point is somewhere in the middle of
the operating region, and it's only a single point. The power and ground
clamp curves, when added together, have to accurately represent the input's
characteristic throughout the device's operating region (0 to VDDQ), if you
want to input to behave properly.
So now the question becomes - where does one curve leave off, and the other
begin? Well, s2ibis2 simply implements the ground clamp curve from -VDDQ to
VDDQ, and the power clamp curve from VDDQ to 2*VDDQ. In theory, you should
be able to just attach the two curves together and get the right result - or
at least, that's the assumption s2ibis2 seems to be operating on. Remember,
because the power clamp curve in IBIS is rail-referenced, a sweep from VDDQ
to 2*VDDQ shows up in the IBIS file as from 0 to -VDDQ.
There are a couple of interesting caveats here. First, s2ibis2 ground clamp
curves actually all end at the same point, which is the [typ] value of VDDQ.
Let's assume that we have an HSTL 1.5 driver, whose power rail can vary by
10%. Thus, the [min] power rail is 1.35V, while the [max] power rail is
1.65V. In this case, the ground clamp data ends at 1.5V in all three cases.
The power clamp curves have the same issue, but in reverse. They are
supposed to sweep from VDDQ to 2*VDDQ. That's 0 to -VDDQ in IBIS terms (the
curves really go from -VDDQ to 0 in the IBIS data, because voltages are
supposed to increase). However, all three curves start at the same point,
which is 2*VDDQ[typ] (-VDDQ[typ] in IBISese), and end at the same point,
which is 0V.
But - and this is a big one - because the power clamp curves are
rail-referenced, 0V means different things in the different cases. It means
1.35V for [min], 1.5V for [typ] and 1.65V for [max]. So - if we adjust for
the rail reference and talk about ground-referenced voltages, the voltage
data points for the power clamp curves range from:
[min] 1.35V to 2.85V
[typ] 1.5V to 3.0V
[max] 1.65V to 3.15V
Let's set those side by side with the ground clamp curves and see what we
get:
Ground Clamp Power Clamp
[min] -1.5V to 1.5V 1.35V to 2.85V
[typ] -1.5V to 1.5V 1.5V to 3.0V
[max] -1.5V to 1.5V 1.65V to 3.15V
The [typ] curves complement each other just fine, but there is an overlap in
the [min] data and a gap in the [max] data. We're primarily concerned about
capturing the behavior of the input termination across the entire operating
region here, so this looks like it might be a problem. Of course, that is
determined by how the simulator handles the situation where the clamp V-I
curves overlap or have a gap in them. We didn't expect what we found,
however.
3) How IBIS simulators use the data in the IBIS models
------------------------------------------------------
Different simulators may well do different things, and I'm not trying to say
I've tested all of them. At least some of them, if not all of them, behave
as I'm describing here.
We suspected an IBIS simulator might "double count" the current in the
overlap region in the [min]case (between 1.35V and 1.5V), thereby making the
termination appear twice as strong as it really was (in that region). We
didn't know what was going to happen in the [max] case, with a cap in the
data between 1.5 and 1.65V. So - we read the models in and tested them.
What we found, empirically, is that the simulator didn't add the curves
together the way you might expect - taking the data from the ground clamp
curve between -VDDQ and VDDQ, and the data from the power clamp curve
between VDDQ and 2*VDDQ. Instead, the simulator *extended each curve by
extrapolation* to cover the entire region from -VDDQ to 2*VDDQ, and *THEN*
added the currents together. In other words, the power clamp curve (which,
at the "IBIS 0V" point, corresponding to VDDQ, has a slope of roughly the
termination value) got extended through the whole operating region with a
slope roughly equal to the termination value. Now, when the simulator added
the contributions of the power and ground clamps in the operating region, it
came up with roughly twice the correct current, making the termination
appear twice as strong as it really was. We started out thinking there
might be a small problem in the gap/overlap regions of the [max/min] curves,
and discovered instead that none of the simulation cases were working
correctly, anywhere in the operating region.
This is a classic case of compartmentalization and assumptions - between
IBIS, s2ibis2 and the IBIS simulators. Bottom line, the basic assumption
was that clamps don't kick in until you go beyond the rail, and the overall
process falls apart in this case as a result.
4) What we can do about it
--------------------------
Again, I'm predicating this on the use of s2ibis2 to create IBIS models.
The goal is simple: create an IBIS model that accurately reproduces the
combined behavior of the clamps and input termination over the range
from -VDDQ to 2*VDDQ.
Both proposals both rely on the same basis: having s2ibis2 perform a single
input V-I sweep, over the voltage range from -VDDQ to 2*VDDQ. That one
simulation would capture all the behavior we're concerned about here. From
there, it's just a matter of how you format the data.
Proposal 1) Says that you put the whole kit & kaboodle into the [GND Clamp]
curve and omit the [POWER Clamp] curve entirely. There's really only one
composite input characteristic, anyway; separating it into two sets of clamp
curves is artificial. Having two curves provides benefits in some cases,
but it's hard to argue that those benefits apply here. This is the easiest
solution to implement, and provides the composite curve in one place. The
downside is that some users might object to having the power clamp data
included in the [GND Clamp] curve, and that some simulation tools might also
have a problem with this. A simulation tool that used a different technique
for combining the curve data might very well have a problem with this
approach.
Proposal 2) ... which Arpad suggested, was to find the zero-current point in
each of the min-typ-max cases, and assign all negative current to the ground
clamp, and all positive current to the power clamp. You need to make sure
that each clamp curve has two consecutive voltage data points with zero
current at the correct end of the curve (so that all further points are zero
current by extrapolation). You also need to do the proper voltage
translations when assigning current to the power clamp curve. The advantage
of this technique is that you end up with two sets of clamp curves as most
people expect, and they add together correctly. This disadvantage is a
slight increase in process complexity, and the fact that you probably won't
be able to view the overall input behavior in one place. Interestingly, the
IBIS-viewer/model-editor tools seem to allow you to view the combined V-I
characteristics of the output buffers, but don't provide for viewing the
combined characteristics of the power and ground clamp curves on an input.
.... so there you have it - s2ibis2 and input termination modeling in IBIS,
as I presently understand it. Corrections to my reasoning, comments and
thoughts on the subject are both welcome and greatly appreciated.
Todd.
Todd Westerhoff
High Speed Design Specialist
Cisco Systems
1414 Massachusetts Ave - Boxboro, MA - 01719
email:twesterh@cisco.com
ph: 978-936-2149
============================================
"When did the choices get so hard, with so much more at stake?
Life gets mighty precious when there's less of it to waste"
- Bonnie Raitt, "Nick of Time"
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This archive was generated by hypermail 2b28 : Fri May 09 2003 - 11:04:03 PDT