[IBIS-Users] Direct input/Output buffer modeling


Subject: [IBIS-Users] Direct input/Output buffer modeling
From: Gang Huo (ghuo@lsil.com)
Date: Fri Jun 27 2003 - 10:14:41 PDT


Hi All,

I am having some issues when generating IBIS models for following kind of
buffers:

                   |----------|
input---- |Protect circuit |---------output
                   |----------|

Basically, output is directly connected to input with the add-on of ESD
protection circuit.

Is the "series" the only good way to model this kind of buffer? Is there a
good way to model this buffer in IBIS spec 2.1?

The problem I met using the "traditional" IBIS model is that the ramp time
won't change with respect to input, but will stay at the value stated in the
IBIS model.

For example, when generating the IBIS model, I use a signal with ramp of
1V/1E-10s on the input to simulate the ramp time. The generated IBIS model
will have a ramp time in the same range. But when doing simulation with the
generated IBIS model, the simulated output will stay at about the same ramp
time (1V/1E-10s), even if I changed the ramp time for the input signal to
(1V/1E-8S), which is not the correct way the buffer works.

Anyone has met the same issues before? Any feedback will be greatly
appreciated.

Thanks,
Gang

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