Subject: RE: [IBIS-Users] IBIS model Error
From: Tom Dagostino (tom@teraspeed.com)
Date: Wed Aug 20 2003 - 14:14:02 PDT
This is quite normal operation for a buffer. All outputs have a finite
output impedance. The output impedance and the load form a voltage divider
so the output voltage will never make it to zero volts when there is a
pullup termination. The output voltage will be
Vout = Vdd * (Rout/(Rout + Rload)
Tom Dagostino
Teraspeed Consulting Group LLC Teraspeed Consulting Group LLC
2926 SE Yamhill St. Device Modeling Division
Portland, OR 97214 13610 SW Harness Lane
Beaverton, OR 97008
http://www.teraspeed.com 503-430-1065
tom@teraspeed.com
-----Original Message-----
From: Allen Chao [mailto:achao@synopsys.COM]
Sent: Wednesday, August 20, 2003 1:59 PM
To: tom@teraspeed.com; ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS model Error
Hi all,
Here is the simplified output buffer of my device... due to the internal
resistor, my falling/rising waveforms are not falling/rising like the sample
IBIS models I found on the internet.
For example, my falling waveform with the 50-ohm load terminated with
different VDD as following are falling from 3.3/2.97/3.63V to 1.5V instead
of 0V. My confusion is whether I should remove the internal resistor or
leave the way it is...
[Falling Waveform]
R_fixture = 50
V_fixture = 3.30
V_fixture_min = 2.97
V_fixture_max = 3.63
Vdd Vdd
_____ ____
| |
| |
- |
___| |
| / \
- ---
| | internal resistor
|-----|---------^v^v^v----------x
| | 45 ohm output(Bond pad)
-
___| |
| / \
- ---
| |
| |
----------------- VSS
Thanks in advance,
Allen Chao
-----Original Message-----
From: Tom Dagostino [mailto:tom@teraspeed.com]
Sent: Wednesday, August 13, 2003 5:55 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error
Allen
The load line is the straight negative sloping line. Where it intersects
the pulldown curves is the calculated end point for that load. This is the
voltage that the parser is predicting. The parser will read the first point
in the rising waveform with a 50 Ohm load to 3.3V table and then compare
this to the load line applied to the pulldown curve. Ideally the two points
should match. The parser will go through all the VT tables and match their
end points (first point and last point in the table) with the predicted
voltages computed from the know load R, known load termination voltage and
the appropriate pullup and pulldown curves (which will include the power and
ground clamps).
A falling waveform in this example will be the falling waveform with 50 Ohms
to 3.3 (as opposed to 50 Ohms to Gnd). The falling waveform will start at
3.3V (the first point in the table) and end at the predicted voltage (the
last point in the table). If the two differ you get either a warning or an
error, depending on the magnitude of the difference.
For the cases where the falling waveform has its load tied to ground then
the fall will start at the level predicted by the load line applied to the
pullup table and end at ground. For both of these examples I'm assuming a
simple CMOS driver with not special features, just a plane pullup and
pulldown with zero current in the clamps in the active region between Gnd
and Vcc.
Tom Dagostino
Teraspeed Consulting Group LLC Teraspeed Consulting Group LLC
2926 SE Yamhill St. Device Modeling Division
Portland, OR 97214 13610 SW Harness Lane
Beaverton, OR 97008
http://www.teraspeed.com 503-430-1065
tom@teraspeed.com
-----Original Message-----
From: Allen Chao [mailto:achao@synopsys.COM]
Sent: Wednesday, August 13, 2003 2:40 PM
To: tom@teraspeed.com
Subject: RE: [IBIS-Users] IBIS model Error
Hi Tom,
Thanks for showing me this. But what does it mean? and what are the DC end
points that should match? Can you also tell me how the falling waveform
should behave in your example?
Allen
-----Original Message-----
From: Tom Dagostino [mailto:tom@teraspeed.com]
Sent: Wednesday, August 13, 2003 4:52 PM
To: 'Allen Chao'
Subject: RE: [IBIS-Users] IBIS model Error
Allen
See the enclosed spreadsheet. I added a 50 Ohm load line terminated to 3.3V
to the pulldown curves in this example
Tom Dagostino
Teraspeed Consulting Group LLC Teraspeed Consulting Group LLC
2926 SE Yamhill St. Device Modeling Division
Portland, OR 97214 13610 SW Harness Lane
Beaverton, OR 97008
http://www.teraspeed.com 503-430-1065
tom@teraspeed.com
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of
Allen Chao
Sent: Wednesday, August 13, 2003 1:38 PM
To: erik.van.der.ven@philips.com; KMuthulakshmi@scmmicro.co.in;
ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS model Error
Hi IBIS experts,
I have the same problem as Muthu Lakshmi. I don't really understand how the
parser calculated the DC end points from the IV table... If anyone can
kindly show me how it works or know where to find the information on the
internet, it will be greatly appreciated.
Thanks in advance,
Allen Chao
-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of
erik.van.der.ven@philips.com
Sent: Monday, July 28, 2003 4:10 AM
To: KMuthulakshmi@scmmicro.co.in; ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS model Error
Hello Muthu Lakshmi,
I think there is something wrong with your IBIS model. The DC end points
calculated from the I-V tables should match the V-T end points (logic
levels). If the error is within 2% you should get a warning, otherwise an
error. The difference you mention is very big.
The DC end points are calculated from the I-V tables (therefore you don't
see the end points of the V-T table). The I-V tables are derived by sweeping
a voltage at the output and measuring the resulting current. By applying a
certain load the voltages from the logic high and low level are calculated
from the pull-up and pull-down curve (and of course they should be near the
waveform end point voltages). The V-T data is used to describe the
transition between the logic levels calculated from the I-V data.
I would suggest that you contact Cypress to ask if this model is OK.
With kind regards,
Ir. Erik van der Ven
Room DB1032
Business Line Networking Infrastructure
Philips Semiconductors BV
Gerstweg 2
6534 AE Nijmegen
The Netherlands
Phone: +31-24-3534334
KMuthulakshmi@scmmicro.co.in
Sent by:
owner-ibis-users@eda.org
07/28/03 05:32 AM
To: ibis-users@eda.org
cc: (bcc: Erik van der Ven/NYM/SC/PHILIPS)
Subject: [IBIS-Users] IBIS model Error
Classification:
Hi All,
I need IBIS expert's advice on the following.
I get the following warning when checking the IBIS model.
Warning - Model bp_usb_hs: The [Rising Waveform]
with [R_fixture]=45 Ohms and [V_fixture]=0V
has TYP column DC endpoints of 0.00V and 0.38v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.14V and 1.06V),
a difference of 99.99% and 64.28%, respectively.
Warning - Model bp_usb_hs: The [Falling Waveform]
with [R_fixture]=45 Ohms and [V_fixture]=0V
has TYP column DC endpoints of 0.00V and 0.38v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.14V and 1.06V),
a difference of 99.99% and 64.28%, respectively.
Warning - Model bp_usb_hs: The [Rising Waveform]
with [R_fixture]=45 Ohms and [V_fixture_min]=0V
has MIN column DC endpoints of 0.00V and 0.37v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.09V and 0.93V),
a difference of 99.99% and 60.23%, respectively.
Warning - Model bp_usb_hs: The [Falling Waveform]
with [R_fixture]=45 Ohms and [V_fixture_min]=0V
has MIN column DC endpoints of 0.00V and 0.37v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.09V and 0.93V),
a difference of 99.99% and 60.23%, respectively.
Warning - Model bp_usb_hs: The [Rising Waveform]
with [R_fixture]=45 Ohms and [V_fixture_max]=0V
has MAX column DC endpoints of 0.00V and 0.39v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.77V and 1.83V),
a difference of 100.00% and 78.72%, respectively.
Warning - Model bp_usb_hs: The [Falling Waveform]
with [R_fixture]=45 Ohms and [V_fixture_max]=0V
has MAX column DC endpoints of 0.00V and 0.38v, but
an equivalent load applied to the model's I-V tables yields
different voltages ( 1.77V and 1.83V),
a difference of 100.00% and 79.26%, respectively.
Please tell me the impact of this warning in simulation. I use XTK for the
simulation. Eventhough the rise and fall VT curve values range from 0V to
0.38V in the IBIS model, I get 1.04V to 1.14V wave form. How is this related
with this. I am using Cypress "CY7C65640" hub controller's IBIS model.
Awaiting your earliest reply.
Note: One IBIS parser gives the above warnings and another parser gives them
as Errors.
I do not know whether files can be attached with this mail. If it is
OK, I can send the IBIS model.
thanks & regards
K.Muthu Lakshmi (KML)
SCM Microsystems (India) Pvt. Ltd.
email: KMuthulakshmi@scmmicro.co.in
Web: www.scmmicro.com
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