RE: [IBIS-Users]Difference in rise-fall waveform due to c_comp!!

Alok,

Sorry for the long delay...

My first question to you is: where did you connect the other end
of the resistor, GND, Vcc, anything in-between, etc? Based on your
results my guess is that you may have had it connected to GND, and
here is why.

Your rising edges are matching with both C_comp values, but falling
edges are different. When the resistor is connected to ground, the
rising edge is mostly due to the pullup turning on (if there is no
significant crow bar current between the pullup and pulldown
transistors). However, the falling edge is mostly due to the pullup
turning off (again if there is no significant crow bar current).
If the buffer is designed so that there are no crow bar currents
between the pu and pd transistors, the transistor that is being
turned off is turned off much faster than the transistor that is
being turned on.

With this background, consider the following: The compensation
algorithm essentially creates a new waveform. If you increase
the C_comp value, this new waveform is going to be steeper (faster)
than the original waveform, because the goal is to end up with a
waveform that matches the original with the additional C_comp
loading. Now, the IBIS V-t curves (waveforms) for the turn-off
transitions are already fairly steep to start with. The
maximum change the compensation algorithm can do to it is
to make it vertical and no more (since we can't go backwards
in time). If your model reaches this limit, the compensation
algorithm will not be able to compensate further, and you will
start seeing differences in the output waveform. I think this is
what you see in case #2.

I am not sure how to explain your #3 and #4 cases with the
capacitive loads, but it may be related to the above reasoning
since a capacitor may not load your buffer heavily enough.

I hope this gives you some insight to what may be happening.

Arpad
==============================================================

-----Original Message-----
From: Alok Rungta [mailto:a0875973@india.ti.com]
Sent: Wednesday, March 03, 2004 12:44 AM
To: Muranyi, Arpad
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users]Difference in rise-fall waveform due to
c_comp!!

Arpad,
I am not sure if I understood things correctly .. First I would further
clarify the experiment I did. I simulated a simple circuit with a
buffer(ibis model) and a load. I tried two loads one resistive and other
only cap. For each load condition I did 2 simulations with different
ibis model files wherein in the 2nd simulation I just changed the
c_comp(made it 10x the actual) value to see the effect of this
parameter on the simulation. What I observe is:

For Resistive load:(which is same as the load I used for generating the
V-t curve in IBIS model):
1>When there is a transition from low to high the waveform in both the
cases(with actual ibis model of the buffer and with the one which has
c_comp modified to 10x) is exactly same.
2>But when there is a fall transition at output the waveforms are
different for two cases.

For Cap load:
3> Waveform is different for the rise case in both the cases.
4> Waveform is different for the fall cases in both the cases.

 From what I understand observation 2 can be explained because of
current flowing in the buffer(outside in) and thus c-comp coming in
picture.observation 1 => no role of c_comp in low to high transition
because its inside out.
Observation 4 can also be attributed to an outside in effect where
c_comp comes into effect. But observation 3 is what I am not very clear
about .. One thing I deduce is that probably the v-t curves in the ibis
model are generated for resistive loads so when it comes to resistive
loads the simulator just uses IV curve and V-t curves in the model for
interpolation and generates the curve(accuracy depending on difference
between the loads you simuated for and load being used in the
simuation). When using the cap. load it cannot possibly use this V-t
curve in the same way because the load is of entirely different nature.
So it has to look at the c-comp. How is it using the IV information in
this case is not very clear to me ?
Can you please throw some more light on this ...

Thanks in Anticipation
Alok Rungta

Muranyi, Arpad wrote:

>Alok,
>
>What you see is the correct behavior.
>
>The meaning of C_comp is die capacitance which includes
>everything that is on the die, pad, metal, transistors,
>etc... When you obtain waveforms (Vt curves), this
>capacitance is in place, so the waveform includes its
>effects. For this reason, IBIS simulators do not use
>this capacitance to load the waveform that is in the
>IBIS model, i.e. no matter what value you provide for
>C_comp, the simulation waveforms will remain the same
>(within reasonable limits) with the same resistive
>load on the output. On the other hand, any external
>capacitance connected to the output of the IBIS model
>will change its simulation waveforms, because that
>will act as a load to the buffer.
>
>On the other hand, the value of C_comp will have an effect
>the reflections which come to the buffer from the outside.
>
>In summary, C_comp is invisible from the inside out, but
>visible from the outside in.
>
>I hope this helps,
>
>Arpad Muranyi
>Intel Corporation
>=========================================================

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Received on Tue Mar 16 12:11:47 2004