RE: [IBIS-Users] IBIS-SPICE correlation

From: Lynne Green <lgreen22@mindspring.com>
Date: Tue Mar 16 2004 - 13:02:52 PST

Prabhu-

Different simulators handle overclocking differently.

Consider the case where the transition takes 0.7nsec, but the V-t table is
20nsec long, and the buffer is toggled with a period of 1nsec. Tool A might
not allow the buffer to toggle before 20nsec has elapsed, no matter what the
toggle rate was supposed to be. Tool B might allow the buffer to toggle
after 1 nsec, no matter how long the V-t table was.

Also, there are various algorithms for toggling part way through the
previous transition. If one needs to handle this situation, then one should
work closely with the tool vendors and make comparisons against bench data.

- Lynne

Lynne Green
Green Streak Programs

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Mohan, Prabhu
Sent: Tuesday, March 16, 2004 11:19 AM
To: Ibis-Users (E-mail)
Subject: RE: [IBIS-Users] IBIS-SPICE correlation

Hi

Over-clocking does seem to be the problem. HSPICE was used in the
correlation.

- But how do the commercial simulators handle this?
- Do they have a way of identifying over-clocking and adjust accordingly?

Thanks everyone for the help.

Prabhu/~

-----Original Message-----
From: Bob Ross [mailto:bob@teraspeed.com]
Sent: Tuesday, March 16, 2004 1:27 AM
To: Mohan, Prabhu
Cc: Ibis-Users (E-mail)
Subject: Re: [IBIS-Users] IBIS-SPICE correlation

Hello Prabhu:

Several people provided some useful observations. It is difficult
to give specific advice without having all the data (IBIS file,
test circuit, simulator used).

However, I suggest checking if "over-clocking" exists per Arpad
Muranyi's response and presentation link below by doing these
tests:

(1) Run the simulation with even a slower cycle time such as an
80 ns period to see if the second cycle rising edge "snaps" into
overlaying correlation.

(2) Or possibly modify the IBIS file itself and truncate
the [Falling Waveform] data to 20 ns or less.

The test condition appears to be a lightly loaded buffer (3.3 V
swing) but the internal tables may be based on R_fixture values
of 50 ohms. One of the falling edge tables may be longer than 20 ns.
The EDA tool should check for transition completion in case the
model waveform tables are documented over a conservatively long
time duration. Either the completion condition is not satisfied
or such a test may not exist. The EDA tool may be assuming an
"over-clocking" condition and cause a "snap" to next edge
transition and lose the edge delay.

Bob Ross
Teraspeed Consulting Group

---------
Arpad Muranyi's response:

Your waveform tables seem to be longer than the pulse
width of your simulation stimulus. Please see my the
first part of my presentation for explanation:

http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf

The clue is that the first edge is correct, but from
the second edge onward you have a shift.

I hope this helps,

Arpad
=========================================================

Mohan, Prabhu wrote:

> Hi
> I am trying to correlate IBIS vs. Spice. The simulation seems to be off on
> the rising edge. IBIS seems to start switching a little bit earlier than
> Spice on the rising edge (refer the attachment, red-IBIS, yellow-SPICE).
I'm
> not sure what is causing it. Does anyone have any suggestion as to where
the
> error might be coming from?
> Thanks
> Prabhu
>

-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Consulting Group LLC
2926 SE Yamhill St.                Device Modeling Division
Portland, OR 97214                 13610 SW Harness Lane
503-239-5536                       Beaverton, OR 97008
http://www.teraspeed.com           503-430-1065
bob@teraspeed.com                  503-246-8048 Direct
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Received on Tue Mar 16 13:02:47 2004

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