RE: [IBIS-Users] IBIS Model Verification

From: Lynne Green <lgreen22@mindspring.com>
Date: Wed Jul 14 2004 - 12:05:58 PDT

Hello, Tess,

I am not sure I understand why one would need to "overcome" strongest clamps
being in "Min" column?

The clamp and driver currents are always correlated under the same operating
conditions (including temperature), so having strongest clamp in Min column
is not uncommon for a model.

- Lynne

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Tess Trethewey
Sent: Wednesday, July 14, 2004 8:48 AM
To: lgreen22@mindspring.com; 'lee yang'
Cc: ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS Model Verification

Lee

Although we check vs. Spice, one additional check we require is that the
clamps be verified against silicon. Many (most) device models (used in
Spice) are checked/guaranteed accurate only in the range [0, Vcc]. What
you'll see in the clamping regions is [-Vcc, 0], [Vcc, 2Vcc] is that one of
two things usually happens:
1. Clamp currents are excessive - more than an amp or so. This is most
common and in simulation can be avoided by adding a small series resistor
(eg. 0.2 ohm)
2. Clamp Min/Typ/Max curves invert so the Min becomes the strongest
clamping. This is usually due to temperature sensitivity in the device
model; to overcome this the device model parameters need to be revisited.
Unfortunately the same problem happens in SPICE, so verifying against the
spice model does not guarantee accuracy.

We haven't found a way to accurately model clamps without either spending
weeks revisiting device model parameters, or (easier) just using a curve
tracer to check the clamps in the lab.

While the pullup and pulldowns silicon measurements are nice to have,
experience shows that the simulated pu/down are fairly accurate; however
the simulated clamps are almost always different and we require that this
check be done.

Hope this helps.

Regards,
Tess Trethewey
Sr Apps Eng, Cypress Seminconductor

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
Behalf Of Lynne Green
Sent: Friday, July 02, 2004 10:32 AM
To: 'lee yang'
Cc: ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS Model Verification

This is so new, that there is no established "accepted percentage".
This will probably be defined by individual "end user" companies.

- Lynne

-----Original Message-----
From: lee yang [mailto:changly_80@hotmail.com]
Sent: Thursday, July 01, 2004 10:52 PM
To: lgreen22@mindspring.com; ibis-users@eda.org
Subject: RE: [IBIS-Users] IBIS Model Verification

Hi Lynne,

Thanks a lot for your information and prompt responce.
Regarding to item 3, let say I am comparing the waveforms between IBIS and
Spice simulations,
besides considering the rise/fall time, should I also compare the waveforms
in terms of the overshoot,undershoot,amplitude? For the rise/fall time, what

is the acceped percentage of
accuracy? (90%???)
Thanks!

Best regards,
L.Y. Chang

>From: "Lynne Green" <lgreen22@mindspring.com>
>Reply-To: <lgreen22@mindspring.com>
>To: "'lee yang'" <changly_80@hotmail.com>, <ibis-users@eda.org>
>Subject: RE: [IBIS-Users] IBIS Model Verification
>Date: Thu, 1 Jul 2004 16:18:24 -0700
>
>Hello, Lee,
>
>1) For checking IBIS against SPICE, there is a method and a FOM (figure of
>merit) documented on the IBIS Quality checklist and document.
>The link is http://www.sisoft.com/ibis-quality/
>
>2) IBIS files should pass the IBIS parser and be tested in at least one SI
>simulator; it sounds like you are already at this point. Additionally, one
>could check the file against the IBIS Quality checklist.
>
>3) Most users expect the models to predict SI performance into a range of
>loads (transmission lines with and without termination). Also important is
>the use of V-t tables to describe internal buffer delays and any asymmetry
>in rise/fall driver characteristics.
>
>As a semiconductor model maker, you might be interested in submitting a
>file
>to the IBIS Review Committee. This committee represents a number of EDA
>tool makers.
>The link is http://www.eigroup.org/ibis/support.htm
>
>Best regards,
>Lynne
>
>
>"IBIS training when you need it, where you need it."
>
>Dr. Lynne Green
>Green Streak Programs
>http://www.greenstreakprograms.com
>425-788-0412
>lgreen22@mindspring.com
>
>
>
>
>-----Original Message-----
>From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
>Of lee yang
>Sent: Wednesday, June 30, 2004 8:11 PM
>To: ibis-users@eda.org
>Subject: [IBIS-Users] IBIS Model Verification
>
>Hi IBIS experts,
>
>I have generated a list of IBIS models and my next task to check whether
>the
>
>generated IBIS models are correlated to the Spice model.I have no idea at
>all how am I going to verify whether the generated IBIS models are
>accurate.
>
>My questions here are:
>1) Does IBIS committee define a standard procedure of verifying the IBIS
>models to see if they are correlated to Spice models? If yes, then where
>can
>
>I get this document?
>2) Normally, how do IBIS providers assure that the IBIS models provided to
>customers are accurate or correlated to Spice model?
>3) What are the criteria to be considered in order to determine the
>accuracy
>
>of an IBIS model compared to Spice model?
>Could anyone please give some help? Detailed explainations are desired as I
>am just a beginner to IBIS world.
>Many thanks.
>
>-L.Y. Chang
>
>_________________________________________________________________
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Received on Wed Jul 14 12:05:47 2004

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