[Fwd: [Fwd: RE: [IBIS-Users] IBIS Model Verification]]

From: Greg Haynes <haynes@aeroflex.com>
Date: Thu Jul 15 2004 - 11:53:19 PDT

I have a few questions about this diode model problem:

1. Which TSMC technologies are affected?
2. What does TSMC say about it (if anything)?
3. How can you work around the problem?

This has a serious impact on IBIS models made from
HSPICE simulations using TSMC models!

-Greg

Greg

I don't know if you got the attachment. It shows the 'shooting off' min
curve, and the actual measured curve. Unfortunately it's not a mising
diode, it's the fact that the diode model breaks down at high temperature in
the high voltage regions (not guaranteed by TSMC), presenting minimal
impedance.

Tess

-----Original Message-----
From: Greg Haynes [mailto:haynes@aeroflex.com]
Sent: Thursday, July 15, 2004 8:20 AM
Cc: tnt@cypress.com; ibis-users@eda.org
Subject: Re: [IBIS-Users] IBIS Model Verification

I'm curious about this min condition clamp behaviour. What do
you mean by "shooting off"? I have had problems with these
simulations and traced them to a missing diode in the extracted
SPICE netlists. Can someone explain this problem a little more?
-Greg

Lynne Green wrote:

>Hi, Tess,
>
>I have seen this from more than one foundry. Indeed, there are two things
>that are poorly modeled by many foundries - diodes in general, and reverse
>leakage in transistor S/D/substrate junctions. This might have to do with
>the fact that devices go into breakdown before models do (i.e. foundries
>have no way to test these parameters over -Vcc to +2Vcc). But some of the
>blame also could be put on the underlying SPICE model equations.
>
>Since well-designed interconnects don't normally swing all the way from
>-Vcc to +2Vcc, it is usually tolerable if the model is less accurate "way
>out there". It is an engineering judgment call over what range of voltage
>the model needs to be highly accurate.
>
>Maybe some people with experience in this area can offer their thoughts.
>
>Best regards,
>Lynne
>
>
>
>"IBIS training when you need it, where you need it."
>
>Dr. Lynne Green
>Green Streak Programs
>http://www.greenstreakprograms.com
>425-788-0412
>lgreen22@mindspring.com
>
>-----Original Message-----
>From: Tess Trethewey [mailto:tnt@cypress.com]
>Sent: Wednesday, July 14, 2004 12:31 PM
>To: lgreen22@mindspring.com
>Cc: ibis-users@eda.org
>Subject: RE: [IBIS-Users] IBIS Model Verification
>
>Lynne
>
>Sorry I wasn't clear. What we see is the min clamp 'shooting off'. When
the
>clamps are actually measured on the silicon, under the same conditions,
this
>behaviour is not seen.
>
>I've attached the original simulation with the measured results. Note that
>the conditions are the same.
>
>Curious, we see this with many standard industry (ie TSMC) models. I'm
>interested to hear from the rest of the group if IC manufacturers run into
>the same problem? What do other people do? We've had a poor response from
>manufacturers as far as generating models accurate outside [0, Vcc], it's
>usually easier to just measure in the lab. Anyone else tried to fight
this?
>
>Tess
>
>-----Original Message-----
>From: Lynne Green [mailto:lgreen22@mindspring.com]
>Sent: Wednesday, July 14, 2004 12:06 PM
>To: tnt@cypress.com
>Cc: ibis-users@eda.org
>Subject: RE: [IBIS-Users] IBIS Model Verification
>
>
>Hello, Tess,
>
>I am not sure I understand why one would need to "overcome" strongest
clamps
>being in "Min" column?
>
>The clamp and driver currents are always correlated under the same
operating
>conditions (including temperature), so having strongest clamp in Min column
>is not uncommon for a model.
>
>- Lynne
>
>-----Original Message-----
>From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
>Of Tess Trethewey
>Sent: Wednesday, July 14, 2004 8:48 AM
>To: lgreen22@mindspring.com; 'lee yang'
>Cc: ibis-users@eda.org
>Subject: RE: [IBIS-Users] IBIS Model Verification
>
>Lee
>
>Although we check vs. Spice, one additional check we require is that the
>clamps be verified against silicon. Many (most) device models (used in
>Spice) are checked/guaranteed accurate only in the range [0, Vcc]. What
>you'll see in the clamping regions is [-Vcc, 0], [Vcc, 2Vcc] is that one of
>two things usually happens:
>1. Clamp currents are excessive - more than an amp or so. This is most
>common and in simulation can be avoided by adding a small series resistor
>(eg. 0.2 ohm)
>2. Clamp Min/Typ/Max curves invert so the Min becomes the strongest
>clamping. This is usually due to temperature sensitivity in the device
>model; to overcome this the device model parameters need to be revisited.
>Unfortunately the same problem happens in SPICE, so verifying against the
>spice model does not guarantee accuracy.
>
>We haven't found a way to accurately model clamps without either spending
>weeks revisiting device model parameters, or (easier) just using a curve
>tracer to check the clamps in the lab.
>
>While the pullup and pulldowns silicon measurements are nice to have,
>experience shows that the simulated pu/down are fairly accurate; however
>the simulated clamps are almost always different and we require that this
>check be done.
>
>Hope this helps.
>
>Regards,
>Tess Trethewey
>Sr Apps Eng, Cypress Seminconductor
>
>
>
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--
Greg Haynes                  mailto:haynes@aeroflex.com
Aeroflex Colorado Springs    http://www.aeroflex.com/radhard
4350 Centennial Blvd         phone: 719 594-8197
Colorado Springs, CO 80907   fax: 719 594-5541
-- 
Greg Haynes                  mailto:haynes@aeroflex.com
Aeroflex Colorado Springs    http://www.aeroflex.com/radhard
4350 Centennial Blvd         phone: 719 594-8197
Colorado Springs, CO 80907   fax: 719 594-5541
-- 
Greg Haynes                  mailto:haynes@aeroflex.com
Aeroflex Colorado Springs    http://www.aeroflex.com/radhard
4350 Centennial Blvd         phone: 719 594-8197
Colorado Springs, CO 80907   fax: 719 594-5541
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Received on Thu Jul 15 11:51:46 2004

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