[IBIS-Users] IBIS Model-Capacitance

From: Ramalakshmi <ramalakshmi@mistralsoftware.com>
Date: Sun Oct 17 2004 - 22:06:32 PDT

Hi

Could you please clarify the relation between the Capacitance Cin value
found in datasheet and the various components Cpkg, Cpin, Ccomp in the ibis
model?

Thanks,
Lakshmi

----- Original Message -----
From: "Jeremy Plunkett" <jeremy@serverworks.com>
To: "RODRIGUEZ_LECONA_RAMIRO" <rlecona@siu.buap.mx>; <ibis-info@eda.org>;
<ibis-users@eda.org>
Sent: Saturday, October 16, 2004 8:04 AM
Subject: RE: [IBIS-Users] V-t curves discussion

> Ramiro,
> there is no intent in the IBIS specification to model the behavior of the
> "core logic" side of the buffer. Most simulators provide facilites to
allow
> driving the buffer model high, driving it low, and in some cases
> tri-stating, although last I checked Hspice at least did a crummy job of
> that (ignoring the Vt curves when transitioning to tristate). You can
> consider it something of a "bonus feature" that in hspice the stimulus
input
> to the buffer model is under your control and can be interfaced to other
> circuitry if you wish to do so.
>
> To take advantage of this, you need to scale the input voltage seen by the
B
> element to have symmetric switching relative to its thresholds. This is
> easy to implement many different ways; a resistor divider or a voltage
> controlled voltage source come to mind immediately. In addition to the
> voltage scaling, you will need to adjust the timing between the B element
> and the original spice netlist to allow for the time required to reach the
> IBIS thresholds vs the spice input threshold (typically 50% of the core
> voltage).
>
> If you simply wish to drive the B element and the original spice netlist
> with matched timing and there is no additional circuitry beyond the
voltage
> sources providing the stimulus, then I suggest you use a 1v swing and a
very
> fast transition time (say 1ps) for the stimulus to the B element, and an
> appropriate (core voltage) swing and transition time for the spice
netlist,
> with the relative delays adjusted so that the B element's 1ps input
> transition occurs as the spice input crosses the 50% level.
>
> If you implement the stimuli this way you should see pretty close to
> matching duty cycle and output timing between the spice and IBIS versions
of
> the buffer, assuming the Vt curves in the IBIS model were not modified
from
> the original data recorded from the spice model. Other tools will produce
> the same result as long as they are set up to preserve the original Vt
curve
> timing (not always the default).
>
> regards,
> Jeremy Plunkett
>
> -----Original Message-----
> From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On
> Behalf Of RODRIGUEZ_LECONA_RAMIRO
> Sent: Friday, October 15, 2004 9:01 AM
> To: ibis-info@eda.org; ibis-users@eda.org
> Subject: [IBIS-Users] V-t curves discussion
>
>
> Arpad, Bob, Tom, Lynne, Aubrey, Giovanni, Nitin:
>
> Thanks for your feedback. I agree the delay differences are generated
by
> the difference of switching thresholds of IBIS model buffer simulated in
> HSPICE and transistor model, because to a output buffer implemented with
> IBIS in HSPICE its input signal is a digital signal with values 0 and 1,
> and its Vinl and Vinh values are 0.2 and 0.8 respectively. This is the
> cause!!
> But, there is an additional problem, those threshold differences
modify
> the duty cycle.
> HSPICE has two keywords that can help to compensate the delay:
rwf_scal
> and fwf_scal. I have been playing with those keywords and the delay is
> compensated but occurs some mismatchs between wave shapes, in the edges of
> course; when I shift the V-t tables to compensate de delay this mismatch
> doesn't occurs!!
> To the IBIS users the delay doesn't represent a problem because they
> don't have a reference to comparate the delay. However the duty cycle is
now
> the problem because it will be modified if the input stimulus transistion
> time is changed.
> Here my questions: Is a IBIS's goal to simulate correctly the duty
> cycle?
> Does PCB engineers need to simulate the correct
duty
> cycle?
> Or Is their job more directed to a electrical
> phenomenoms (electrical or electromagnetic behavior)?
> If it is necessary to simulate correctly the duty cycle using IBIS
then
> I have a new problem because I can correct it to use it in HSPICE (in
> addition I will have to write notes about valid rise/fall times) but if
the
> IBIS model is simulated in other tool maybe this correction is not going
to
> work.
>
> Thanks.
>
> Regards,
>
> Ramiro Rodriguez
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Received on Sun Oct 17 22:10:51 2004

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