[IBIS-Users] RE: [IBIS-Users] Re : [IBIS-Users] RE: IBIS Model-Capacitance

From: Tom Dagostino <tom@teraspeed.com>
Date: Tue Oct 26 2004 - 02:29:45 PDT

C_comp represents the capacitance on the die associated with the I/O buffer
modeled. I think most of this is between metal in the buffer and the
power/ground in the die. There is some associated with the FETs in the
buffer also.

C_pkg is associated with the package

C_pin is the individual pin parasitic capacitance.

But with Power Integrity you should also look at the capacitance between
metal layers on the chip, specifically between the power and ground layers
on the chip. This capacitance is not in the IBIS model.

Tom Dagostino
Teraspeed Consulting Group LLC
503-430-1065
tom@teraspeed.com
www.teraspeed.com

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org]On Behalf Of
Frank Y.C. Pai
Sent: Monday, October 25, 2004 11:42 PM
To: Mirmak, Michael
Cc: ibis-info@eda.org; ibis-users@eda.org; owner-ibis-users@eda.org;
Ramalakshmi
Subject: [IBIS-Users] Re : [IBIS-Users] RE: IBIS Model-Capacitance

Hi ! Michael and all

I have read your discussion for a long time and get a lot of useful
information. Thank you very much.

And I have a question regarding the Capacitance in IBIS model. Please help
me to clarify it. Thanks.

When power intgerity simulation of board level is performed, the "on-die"
capacitance is an important issue except bulk, bypass, decoupling
capacitors, and plane effects.
In your opinion, C_pin, C_pkg, and C_comp, which one could we use to model
the on-die capacitance?

Thanks.

Regards

Frank Y.C. Pai

___________________________________________________________________________

Simulation Center/PCEG/Foxconn
1) 2, TZU YU St., TU-CHENG CITY, TAIPEI Hsien, 23644, Taiwan, R.O.C.
       Tel: 886-2-22683466 Ext 3419
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___________________________________________________________________________

|---------+--------------------------->
| | "Mirmak, |
| | Michael" |
| | <michael.mirmak@|
| | intel.com> |
| | 寄件人: |
| | owner-ibis-users|
| | @eda.org |
| | |
| | |
| | 2004/10/18 11:44|
| | PM |
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>-------------------------------------------------------------------------
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  | 收件人: "Ramalakshmi" <ramalakshmi@mistralsoftware.com>,
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  | 副本抄送:
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  | 主旨: [IBIS-Users] RE: IBIS Model-Capacitance
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Lakshmi,

Thank you for your interest in IBIS! Definitions of "Cin" may vary from
datasheet to datasheet, so please consult the text of your specific sheets
of interest for details. In general, "Cin" often refers to the total
capacitance "seen" by a signal at the pin of the device and may include
buffer effects.

>From an IBIS perspective, the three quantities you mention can be defined
as follows:

C_pin: the capacitive portion of the package model lumped RLC network
associated with a particular pin in an IBIS [Pin] list; this value should
not include buffer effects

C_pkg: the capacitive portion of the package model lumped RLC network
associated, through the [Package] keyword, by default with all pins of an
IBIS [Component]; this value should not include buffer effects and is
overridden by C_pin, if C_pin is used

C_comp: the total capacitance of a buffer alone from the pad "looking into"
the device, not including package effects; C_comp is found under the
[Model] keyword

I hope this helps!

- Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

-----Original Message-----
From: owner-ibis-info@eda.org [mailto:owner-ibis-info@eda.org] On Behalf Of
Ramalakshmi
Sent: Sunday, October 17, 2004 10:07 PM
To: ibis-info@eda.org; ibis-users@eda.org
Subject: IBIS Model-Capacitance

Hi

Could you please clarify the relation between the Capacitance Cin value
found in datasheet and the various components Cpkg, Cpin, Ccomp in the ibis
model?

Thanks,
Lakshmi

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Received on Tue Oct 26 02:31:38 2004

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