Date: Thu Mar 03 2005 - 12:08:55 PST
Hello experts : I just modeled an I/O buffer and trying to validate my model using HSPICE. Brief setup of IBIS model : 1) [Ramp] was done with 50 ohm to VSS for rising; 50 ohm to VDD for falling ramp. 2) I added four waveform tables since four are needed to dequately describe a CMOS buffer as follows : a) [Rising Waveform] with 50-ohm to VSS = 0.0V b) [Falling Waveform] with 50-ohm to VSS = 0.0V c) [Rising Waveform] with 50-ohm to VDD = 3.3V +/- 10% d) [Falling Waveform] with 50-ohm to VDD = 3.3V +/- 10% After model was complete, I ran a validation simulation using HSPICE with the model instantiated as follows : ______________________________________________________________________ B_IO nd_pu nd_pd nd_out nd_in nd_en v_out_of_in nd_pc nd_gc + file = '../ibis_models/zspcixio_raw.ibs' + model = 'ZSPCIXIO' + typ = 'typ' $ choose typ = [typ/min/max] + buffer= input_output + power = on $ [on] connects nd_pu/nd_pd/nd_pc/nd_gc to power sources in ibis. + interpol = 2 $ 1=linear interpolation, 2=quadratic bi-spline interpolation. + ramp_rwf = 2 $ Rising: 0-use ramp, 1-use 1st waveform data, 2=use two waveforms + ramp_fwf = 2 $ Falling: 0-use ramp, 1-use 1st waveform data, 2=use two waveform + nowarn _________________________________________________________________________ Attached is brief model (with tables removed) and two validation waveforms. Question : 1) First validation plot below has R_fixture = 50, V_fixture = 0.0 to match my 1st [Rising Waveform]. Red line is Spice / Cyan color is IBIS model. I don't understand why the IBIS waveform has rail-to-rail levels (0.0-3.3V). Spice makes sense because my V_fixture = 0.0, and this would decrease the high level. It looks like IBIS runs the combination of all four waveform tables and looks at initial & final voltage values and uses full logic swings. Or : It could be my Voltage Range telling IBIS to always use these full logic swings, so perhaps it's correct ?? [Voltage Range] 3.3000V 2.9700V 3.6300V 2) 2nd validation plot has 100-ohm to Vdd/2 = 1.65V. I did that to get wider logic on Spice output (red line). Now the levels are closer but slews are still off. Please let me know if there is a proper procedure to do this validation, i.e. : Given what I modeled above for the four V-t tables in IBIS with 50-ohm to VDD/VSS, what is a fair hookup to validate this model in Spice with matching slew rates ? Thanks Doran David |************************************************************************ | * zspcixio.ibs * IBIS Model for PCI-X Bidirectional I/O Cell |************************************************************************ [IBIS ver] 4.0 [File name] zspcixio_raw.ibs [File Rev] 0.2 [Date] March 3, 2005 [Source] HSPICE Simulations using HSPICE version W-2004.09 | [Notes] - Used 250ps input slew used for all Ramp & Waveform measurements. - For [Ramp] and [* Waveform] measurements, this model uses the IBIS standard load of 50-ohm to VSS/VDDS for rising/falling, respectively. Four waveforms are included for the V-t tables under [* Waveform]. - All subparameters under [Model spec] are from Toshiba datasheet, and new format is used with rising & falling values. - Package & Pin R/L/C per customer specific model. | [Disclaimer] - none. | [Copyright] Copyright 2005, Toshiba America Electronic Components, All rights reserved. | |************************************************************************ | Component TC280C |************************************************************************ [Component] TC280C [Manufacturer] Toshiba America Electronic Components [Package] | variable typ min max | ----------- ----------- ----------- R_pkg 0.0ohm NA NA L_pkg 0.0nH NA NA C_pkg 0.0pF NA NA | [Pin] signal_name model_name R_pin L_pin C_pin | --- ----------- ---------- ----------- ----------- ----------- A1 PCI_AD32 ZSPCIXIO | |************************************************************************ | Model ZSPCIXIO |************************************************************************ | [Model] ZSPCIXIO Model_type I/O Polarity Non-Inverting Enable Active-High | | Note the next three subparameters are required for [Model], but they | get overridden by same subparameters under [Model spec]. Vinl = 1.155V | Input logic "low" DC voltage Vinh = 1.650V | Input logic "high" DC voltage Vmeas = 1.980V | Ref. voltage for timing measurements | | variable typ min max | ------ ------ ------ C_comp 2.83pF 2.32pF 2.91pF | [Model spec] | variable typ min max | ------ ------ ------ Vinl 1.155V 1.0395V 1.2705V | max 35% VDDS Vinh 1.650V 1.485V 1.815V | min 50% VDDS | Vmeas_rising 0.9900 0.891 1.089 | Vmeas = 0.30(VDDS) Vmeas_falling 1.9800 1.782 2.178 | Vmeas = 0.60(VDDS) | Cref_rising 10p 10p 10p Cref_falling 10p 10p 10p | Rref_rising 25 25 25 Rref_falling 25 25 25 | Vref_rising 0.00V 0.00V 0.00V Vref_falling 3.30V 2.97V 3.63V | [Temperature Range] 25C 125C 0.0C [Voltage Range] 3.3000V 2.9700V 3.6300V | [Pulldown] | Voltage I(typ) I(min) I(max) | ----------- ----------- ----------- ---------- -3.300 -713.179m -744.000m -710.939m 6.600 585.941m 666.035m 524.812m | [Pullup] | *** Note: Vtable = VDDS - Voutput *** | | Voltage I(typ) I(min) I(max) | ----------- ----------- ----------- ---------- -3.300 548.162m 644.593m 472.839m 6.600 -728.438m -752.741m -732.782m | [GND_clamp] | Voltage I(typ) I(min) I(max) | ---------- ----------- --------- --------- -3.300 -712.407m -743.507m -710.052m -3.233 -693.094m -724.289m -690.715m 3.233 4.268u 6.110u 4.268u 3.300 4.356u 8.262u 4.356u | [POWER_clamp] | *** Note: Vtable = VDDS - Voutput *** | Voltage I(typ) I(min) I(max) | -------- ---------- --------- --------- -3.300 547.775m 644.333m 472.333m -33.333m 4.400u 14.249u 4.400u 0.000 0.000u 0.000u 0.000u | [Ramp] | variable typ min max | -------- -------------- -------------- -------------- dV/dt_r 1.371V/0.317ns 1.055V/0.610ns 1.592V/0.258ns dV/dt_f 1.549V/0.277ns 1.235V/0.585ns 1.758V/0.204ns R_load = 50 | [Rising Waveform] R_fixture = 50ohm V_fixture = 0.0000V V_fixture_min = 0.0000V V_fixture_max = 0.0000V C_fixture = 10.0pF | L_fixture = 0.01nH | R_dut = 0.01ohm | L_dut = 0.01nH | C_dut = 0.01pF | | time V(typ) V(min) V(max) | ---------- --------- --------- -------- 0.000 0. 0. 0. 100.000p 0. 0. 0. 200.000p 0. 0. 0. 300.000p 64.831p 0. 3.826u 5.900n 2.285 1.757 2.653 6.000n 2.285 1.757 2.653 | [Falling Waveform] R_fixture = 50ohm V_fixture = 0.0000V V_fixture_min = 0.0000V V_fixture_max = 0.0000V C_fixture = 10.0pF | L_fixture = 0.01nH | R_dut = 0.01ohm | L_dut = 0.01nH | C_dut = 0.01pF | | time V(typ) V(min) V(max) | ---------- --------- --------- -------- 0.000 2.285 1.759 2.653 100.000p 2.285 1.759 2.653 200.000p 2.285 1.759 2.653 6.000n 2.633u 14.854u -3.771u | [Rising Waveform] R_fixture = 50ohm V_fixture = 3.3000V V_fixture_min = 2.9700V V_fixture_max = 3.6300V C_fixture = 10.0pF | L_fixture = 0.01nH | R_dut = 0.01ohm | L_dut = 0.01nH | C_dut = 0.01pF | | time V(typ) V(min) V(max) | ---------- --------- --------- -------- 0.000 717.713m 911.222m 700.180m 100.000p 717.713m 911.222m 700.180m 200.000p 717.713m 911.223m 700.180m 5.900n 3.300 2.970 3.630 6.000n 3.300 2.970 3.630 | [Falling Waveform] R_fixture = 50ohm V_fixture = 3.3000V V_fixture_min = 2.9700V V_fixture_max = 3.6300V C_fixture = 10.0pF | L_fixture = 0.01nH | R_dut = 0.01ohm | L_dut = 0.01nH | C_dut = 0.01pF | | time V(typ) V(min) V(max) | ---------- --------- --------- -------- 0.000 3.300 2.970 3.630 6.000n 717.768m 913.484m 700.195m | | End [Model spec] | End [Model] ZSPCIXIO | End [Component] | [End] IBISCHK4 V4.0.2 Checking zspcixio_raw.ibs for IBIS 4.0 Compatibility... WARNING - Model ZSPCIXIO: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 1.75v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.02V and 1.60V), a difference of 1.09% and 9.27%, respectively. ERROR - Model ZSPCIXIO: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=2.97V has MIN column DC endpoints of 0.91V and 2.97v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.93V and 2.76V), a difference of 1.03% and 11.78%, respectively. WARNING - Model ZSPCIXIO: The [Falling Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=0V has MIN column DC endpoints of 0.00V and 1.76v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.02V and 1.60V), a difference of 1.09% and 10.03%, respectively. ERROR - Model ZSPCIXIO: The [Falling Waveform] with [R_fixture]=50 Ohms and [V_fixture_min]=2.97V has MIN column DC endpoints of 0.92V and 2.97v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.93V and 2.76V), a difference of 0.47% and 11.78%, respectively. WARNING - Model ZSPCIXIO: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=0V has MAX column DC endpoints of 0.00V and 2.65v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.00V and 2.89V), a difference of 0.15% and 8.09%, respectively. WARNING - Model ZSPCIXIO: The [Rising Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=3.63V has MAX column DC endpoints of 0.70V and 3.63v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.71V and 3.88V), a difference of 0.16% and 7.76%, respectively. WARNING - Model ZSPCIXIO: The [Falling Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=0V has MAX column DC endpoints of -0.00V and 2.65v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.00V and 2.89V), a difference of 0.15% and 8.09%, respectively. WARNING - Model ZSPCIXIO: The [Falling Waveform] with [R_fixture]=50 Ohms and [V_fixture_max]=3.63V has MAX column DC endpoints of 0.70V and 3.63v, but an equivalent load applied to the model's I-V tables yields different voltages ( 0.71V and 3.88V), a difference of 0.16% and 7.76%, respectively. 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