RE: [IBIS-Users] delay problem

Hi Ambarish

I am attaching the replies I got for the same question a while ago.
Looks like you have a similar issue. 
Hope this helps.
Prabhu/~



___snip_________________________________________________________________
_____ 
 
	-----Original Message-----

	From: Bob Ross [mailto:bob@teraspeed.com
<mailto:bob@teraspeed.com> ]
	Sent: Tuesday, March 16, 2004 1:27 AM
	To: Mohan, Prabhu
	Cc: Ibis-Users (E-mail)
	Subject: Re: [IBIS-Users] IBIS-SPICE correlation

	Hello Prabhu:

	Several people provided some useful observations. It is
difficult
	to give specific advice without having all the data (IBIS file,
	test circuit, simulator used).
	However, I suggest checking if "over-clocking" exists per Arpad
	Muranyi's response and presentation link below by doing these
	tests:

	(1) Run the simulation with even a slower cycle time such as an
	80 ns period to see if the second cycle rising edge "snaps" into
	overlaying correlation.
	(2) Or possibly modify the IBIS file itself and truncate
	the [Falling Waveform] data to 20 ns or less.
	The test condition appears to be a lightly loaded buffer (3.3 V
	swing) but the internal tables may be based on R_fixture values
	of 50 ohms. One of the falling edge tables may be longer than 20
ns.
	The EDA tool should check for transition completion in case the
	model waveform tables are documented over a conservatively long
	time duration. Either the completion condition is not satisfied
	or such a test may not exist. The EDA tool may be assuming an
	"over-clocking" condition and cause a "snap" to next edge
	transition and lose the edge delay.

	Bob Ross
	Teraspeed Consulting Group

	---------

	Arpad Muranyi's response:

	Your waveform tables seem to be longer than the pulse
	width of your simulation stimulus. Please see my the
	first part of my presentation for explanation:
	http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf
<http://www.eda.org/pub/ibis/summits/jun03b/muranyi2.pdf> 

	The clue is that the first edge is correct, but from
	the second edge onward you have a shift.
	I hope this helps,

	Arpad

___snip_________________________________________________________________
_____ 
 

________________________________

From: Ambrish Varma [mailto:akvarma@ncsu.edu] 
Sent: Tuesday, April 05, 2005 4:00 PM
To: ibis-users@eda.org
Cc: ibis@eda.org
Subject: [IBIS-Users] delay problem



Hello,

I know this problem has been asked several times and answered several
times as well.

So my apologies in advance.

 

Attached is a comparison of hspice and ibis circuits. I want to know 

a)       Why there is a delay at the falling edge.

b)       Where delay information is stored in an IBIS model, if at all.

c)       Does it matter to have a delay? The periods seem to match up.

The IBIS model is created from hspice netlist.

 

Thanks for any feedback,

Regards, 

Ambrish.

 

Ambrish K Varma

akvarma@ncsu.edu

North Carolina State University

ph(919)513-2015, fax(919)515-2285

 


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