RE: [IBIS-Users] question on including package models in IBIS file

David 

The package model values you cite in the [Package] section are the
global  min/max/nominal values for the package without respect to any
particular pin and apply all the silicon models in the .ibs file. It
tells you what the corner cases are for the longest and shortest traces
but not what the package parasitics are for any particular pin.

You could have separate package models with per pin RLC values defined
for each particular silicon model (if that made sense in your
application).

Typically if you have different size die in a particular package size
then you would have different per-pin  RLC data. This per-pin data can
be included either in the .ibs file or in an external .pkg file.

-Ray


Raymond Anderson
Senior Signal Integrity Staff Engineer
Product Technology Department
Advanced Package R&D
Xilinx Inc.
 


-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of CW - Doran David
Sent: Thursday, May 12, 2005 11:09 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] question on including package models in IBIS file

Below is a model for IVDS receiver containing a package 
model which I'm not sure makes sense to include.

In general, we have not included package in the ibis models because
packages differ from project to project.  If I include the package
model in IBIS, I worry that it makes the model specific to one design.

However, it seems that the package model is only under the 
component section and is only for that component, not for 
the LVDS models "LV16TR1P" and "LV16TR1N".

So perhaps it's OK to keep the package model inside this 
LVDS buffer since it's really associated with a component
"DDP3" rather than my LVDS models.

Please let me know ant comments or suggestions how this is 
generally handled - whether or not to include package model
in all IBIS models.

Thanks!


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