RE: [IBIS-Users] IBIS Question

Hi Andy,

 

You have to be careful trying to model to model the PDS in this way.  While
the lumped, low frequency loop inductance approximation of the signal nets
with respect to their reference can be reasonably captured, the same cannot
always be said for power and ground pins.  Trying to model these structures
with a partial inductance approach can be tricky, as the mutuals must be
included for the partials to be meaningful.  Also, depending on your current
transients and frequencies of interest, a linear PDS model simply may not be
appropriate.

 

If you want to move beyond the ideal power supply regime, care must be taken
to model the PDS appropriately.  You'll want to include the frequency
dependent coupling between the signals and the PDS as well, in order to
fully characterize the SSO effects on your system.

 

Please let me know if you have any questions on this.  Thanks!

 

Sam

 

 

  _____  

From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On Behalf
Of Andy Joe
Sent: Wednesday, July 27, 2005 4:18 AM
To: ibis-users@eda.org
Subject: [IBIS-Users] IBIS Question

 

Hi,

 

I have a question regarding the [Package] keyword in an IBIS file. As far as
I am concerned, the RLC values in this section applied to all the I/O pins,
my question is if these RLC values also applied to power and ground pins as
well? If they are not applied to power and ground pins, how can we address
the effects of different packages to the power and ground pins in an IBIS
model? (If R_pin, L_pin and C_pin for every single pin are not available,
only package min, typ and max RLC are available)

Thanks.

 

-Andy

  _____  

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