AW: [IBIS-Users] How to replace RLC package

From: Koller, Katja <katja.koller_at_.....>
Date: Fri Mar 24 2006 - 07:00:15 PST
Hello Radovan,

as far as I have looked at the keyword External Model and
packages I found the possibility to use Series Elements. 
But unfortunately they are not yet supported by our simulation tool...

As for your Circuit Call I think you attached a package to the pins
for vcc and gnd, but not on the pin with the IO. Well, yes it is
attached, but in parallel and not as series.
With circuit call I can think at the moment only to include the
spice-package into the hspice-model.

Regards,
Katja


> -----Ursprüngliche Nachricht-----
> Von: owner-ibis-users@eda.org 
> [mailto:owner-ibis-users@eda.org] Im Auftrag von 
> Radovan.Vuletic@infineon.com
> Gesendet: Freitag, 24. März 2006 15:35
> An: ibis-users@eda.org
> Betreff: RE: [IBIS-Users] How to replace RLC package
> 
> Many thanks to Weston, Lynn and Michael who have answered on 
> my question.
> 
> Unfortunately, since in IBIS specs 4.1 there is no example 
> for that what I need (of course, it is not possible to cover 
> everything) I have created a small (very simplified) 
> component IBIS model where I have replaced (at least that is 
> what I think) lumped RLC in [Pin] section with external 
> HSpice circuit that contains RLC couplings.
> Could you please take a look on it (below) and verify that I 
> am thinking correctly (especial for the section where is a 
> call external circuit). To keep it short as possible I have 
> deleted [Pulldown], [Pullup], [GND_Clamp], [Power_Clamp], 
> [Ramp], [Rising Waveform] and [Falling Waveform]  - you can 
> find the whole IBIS file (test.ibs) in the attachment, as 
> well as HSpice model of package (test_package.net). Btw. I 
> have checked the IBIS model spelling checker IBISCHK4 V4.1.1 
> and there are no warnings or errors - but still, I am not 
> sure that I have done everything properly ... Somehow I have 
> a feeling that I am missing a point. Unfortunately, I can't 
> test it with simulator, because I have first to find one that 
> supports IBIS 4.1. - once agin, many thanks for any answer.
> 
> [IBIS ver]      4.1
> [File name]   test.ibs
> [File Rev]      1.0
> [Date]           Friday, 24 March 2006 
> [Source]       Simulation of a silicon level SPICE model 
> [Notes]         Test model for checking IBIS 4.1 Multi-lingual
>                     Model Extensions
> [Disclaimer]   Just a test
> [Copyright]    (C) Copyright 2006 by Unknown 
> |
> |*************************************************************
> ***********
> |                        Component XYZ
> |*************************************************************
> ***********
> |
> [Component]      XXX
> [Manufacturer]   Unknown
> |
> [Package]
> |                typ                 min                 max
> R_pkg        2.0E-01Ohm  1.0E-01Ohm     3.0E-01Ohm      
> L_pkg        2.0E-09H       1.0E-09H          3.0E-09H  
> C_pkg        2.0E-13F       1.0E-13F          3.0E-13F  
> |
> [Pin]   signal_name  model_name      R_pin           L_pin    
>        C_pin
> |
> A1      VDDQ_A1      POWER           1.0E-01     1.0E-09      1.0E-13
> A2      DQ                Data_IO            2.0E-01     
> 2.0E-09      2.0E-13
> A3      VSSQ_A3      GND                3.0E-01     3.0E-09   
>    3.0E-13
> [Circuit Call] TEST_PACKAGE
> Port_map   vddq_pad_a1  A1
> Port_map      dq_pad_a2  A2
> Port_map   vssq_pad_a3  A3
> Port_map   vddq_ball_a1  A1
> Port_map      dq_ball_a2  A2
> Port_map   vssq_ball_a3  A3 
> Port_map   pkg_ref_gnd   A3
> [End Circuit Call]
> |
> |*************************************************************
> ***********
> |                             Model Data_IO
> |*************************************************************
> ***********
> |
> [Model]          Data_IO
> Model_type       I/O
> Polarity         Non-Inverting
> Enable           Active-High
> [Pulldown]
> [Pullup]
> [GND_clamp]
> [POWER_clamp]
> [Ramp]
> [Rising Waveform]
> [Rising Waveform]
> [Falling Waveform]
> [Falling Waveform]
> |
> | End [Component] XYZ
> |
> [External Circuit] TEST_PACKAGE
> Language SPICE
> Corner Typ test_package.net package_test
> Ports vddq_ball_a1 dq_ball_a2 vssq_ball_a3 vddq_pad_a1 
> dq_pad_a2 vssq_pad_a3 pkg_ref_gnd
> [End External Circuit]
> [End]
> 
> Regards,
> Radovan
> 
> -----Original Message-----
> From: owner-ibis-users@eda.org 
> [mailto:owner-ibis-users@eda.org] On Behalf Of Vuletic 
> Radovan (MP PD PDE)
> Sent: Thursday, March 23, 2006 5:15 PM
> To: ibis-users@eda.org
> Subject: [IBIS-Users] How to replace RLC package
> 
> Hi experts,
> 
> once again (almost) the same question, but now other way around ...
> 
> Recently I am getting lot of pressure to figure out how (in 
> which format) to generate reasonable package model for IBIS 
> models of our components.
> 
> Possible solutions:
> ==============
> 1.) [Sparse Matrix] - contra: tools that generate [Sparse 
> Matrix] models can't generate models for multidrop networks 
> (i.e. one pin one the input, more than one pads on output), 
> sloppy support from simulation tools
> 2.) ICM - contra: no available tool for automated extraction 
> (and nobody wants to do it manually :-(((()
> 3.) Simple RLC parameters - contra: no information about 
> cross-coupling RLC elements (coupling capacitances, mutual 
> inductances, etc.)
> 
> Workaround: use HSpice model of package, but how to "connect" 
> it with IBIS model?
> 
> IBIS 4.1 provides new keywords [External Circuit], [End 
> External Circuit], [External Model], [End External Model] 
> [Node Declarations], [End Node Declarations], [Circuit Call] 
> and [End Circuit Call] to support multi-lingual models - nice! 
> Main question:
> Is there a possibility to replace package description in 
> [Pin] section of [Component] with some [External Circuit] or 
> [External Model] or [Node Declarations]?
> So what I want to do is to replace:
> [Pin]  signal_name   model_name    R_pin        L_pin       C_pin
> |
> A1     VDD           POWER          210m       4.07nH      0.27pF
> A2     NF            NF_INPUT       168m       2.70nH      0.19pF
> .
> .
> .
> T8     VSS           GND            127m       1.45nH      0.23pF
> T9     VSSQ          GND            151m       2.18nH      0.13pF
> 
> With a call to HSpice netlist
> 
> [Circuit Call]
> Pointer to HSpice model of package
> [End Circuit Call]
> 
> Or 
> 
> [External Circuit]
> Pointer to HSpice model of package
> [End External Circuit]
> 
> Allows IBIS 4.1 something like that - is IBIS 4.1 planed for 
> something like that at all?
> 
> When  I take a look (please see below) on a Figure 1 provided 
> in IBIS specs, I am not sure that it is possible.
> 
> | The placement of these keywords within the hierarchy of 
> IBIS is shown 
> | in the following diagram:
> |
> |
> |   |-- [Component]
> |   |   | ...
> |   |   |-- [Node Declarations]
> |   |   |-- [End Node Declarations]
> |   |   | ...
> |   |   | ...
> |   |   |-- [Circuit Call]
> |   |   |-- [End Circuit Call]
> |   |   | ...
> |   | ...
> |   |-- [Model]
> |   |   | ...
> |   |   |-- [External Model]
> |   |   |-- [End External Model]
> |   |   | ...
> |   | ...
> |   |-- [External Circuit]
> |   |-- [End External Circuit]
> |   | ...
> 
> Has anybody some idea about it?
> 
> Many thanks for every answer!
> 
> Best regards / Mit freundlichen Grüßen / S po¹tovanjem Radovan Vuletiæ
> 
> Infineon Technologies AG
> MP PD PDE
> MUC/10.2.236 AP 3
> Am Campeon 1-12
> D-85579 Neuebiberg
> 
> Phone:		+49 (0)89 234 20108
> Fax (PC):	+49 (0)89 234 955 5305 
> 
> E-mail: radovan.vuletic@infineon.com
> 
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Received on Fri Mar 24 07:00:24 2006

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