[IBIS-Users] Re: [IBIS] Open drain strange behaviour

Hello Lynne

  I have this delay (the shape of two waveforms is the same) only for 
Open Drain buffer
  and not for a DATA Buffer.
  Moreover the input signal is the same (with an equal ramp) and the 
Ibis model used has,
  as falling and rising waveform tables, the result of transistor level 
simulation, that
  I am considering  for comparison.

 Thanks and best regards

    Roberto

Lynne D. Green wrote:

>Hello, Roberto,
>
>One of the first questions to ask oneself is: how does the shape of the two
>waveforms differ?  If your SI tool's waveform matches your SPICE waveform
>with a time offset, your are probably seeing an effect of how the buffer
>DATA (from chip core) is triggered.
>
>In SPICE, waveforms show Time from Time=0 (which is start of simulation).
>But any "step" input is actually a ramp between two simulation time steps.
>This ramp rate can vary between simulations, since the time step depends on
>the "stop time" and other .OPTIONS settings.
>
>In many SI simulators, the buffer's DATA "trigger" is a fixed ramp.  The
>ramp slope and trigger level for the buffer DATA are different between
>simulators.
>
>The result is that simulators, from SPICE to SI tool1 to SI tool2, etc,
>will each produce a different Time offset,   but the waveform shape should
>match (for the same R_fixture load).
>
>If your waveforms do not match, then you have a different problem.  In that
>case, you might wish to submit your model to the IBIS Model Review Committee
>for feedback (http://www.eigroup.org/ibis/support.htm).
>
>Best regards,
>Lynne
>
>
>"IBIS training when you need it, where you need it."
>
>Dr. Lynne Green
>Green Streak Programs
>http://www.greenstreakprograms.com
>425-788-0412
>lgreen22@mindspring.com
>
>
>-----Original Message-----
>From: owner-ibis@eda.org [mailto:owner-ibis@eda.org] On Behalf Of Roberto
>IZZI
>Sent: Monday, September 11, 2006 5:17 AM
>To: ibis@eda-stds.org; ibis-users@eda.org
>Subject: [IBIS] Open drain strange behaviour
>
>Hello everybody
>
>  I 'd like to have some information about a strange behaviour of Open drain
>buffer
>  Ibis model. I have noticed a mismatch between Transistor level and Ibis
>model
>  voltage output during a transient analysis. In fact in presence of the
>same input voltage
>  wave and the same value of load resistance (for example 70 ohm),
>  we can observe a delay between TL output and Ibis output. This delay is
>the same
>  if we change the value of  load resistance. What is the cause of this
>strange behaviour?
>
>  Thanks and best regards
>
>        Roberto Izzi
>
>
>
>  
>

--------------------------------------------------------------------
|For help or to subscribe/unsubscribe, e-mail majordomo@eda-stds.org
|with the appropriate command message(s) in the body:
|
|  help
|  subscribe   ibis       <optional e-mail address, if different>
|  subscribe   ibis-users <optional e-mail address, if different>
|  unsubscribe ibis       <optional e-mail address, if different>
|  unsubscribe ibis-users <optional e-mail address, if different>
|
|or e-mail a request to ibis-request@eda-stds.org.
|
|IBIS reflector archives exist under:
|
|  http://www.eda-stds.org/pub/ibis/email_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/users_archive/ Recent
|  http://www.eda-stds.org/pub/ibis/email/         E-mail since 1993