[IBIS-Users] Agenda - Asian IBIS Summit (Japan)

To all attendees of the Asian IBIS Summit (Japan) October 31:

We are very much looking forward to seeing you next week.  Please make
sure that you arrive allowing sufficient time to sign in before the
presentations begin.

Business cards will serve as meeting badges.  

See you in Tokyo!

  Takeshi Watanabe
  NEC Electronics Corp.
  Chair, JEITA EDA Working Group

  Michael Mirmak
  Intel Corp.
  Chair, EIA IBIS Open Forum

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     A S I A N   I B I S   S U M M I T    I N F O R M A T I O N

Time/Date:  8:30 - 15:00, Tuesday, October 31, 2006

Location:   JEITA Headquarters
            3rd Fl., Mitsui Sumitomo Kaijo Bldg. Annex 11,
            Kanda Surugadai 3-chome, Chiyoda-ku,
            Tokyo 101-0062
            JAPAN

            http://www.jeita.or.jp/english/about/location/index.htm

Registration:  FREE, send to both addresses below:
            Name:
            E-mail address:
            Company:
            Telephone:

     Bob Ross, Teraspeed Consulting Group    bob@teraspeed.com
     Takeshi Watanabe, NEC Electronics Corp. takeshi.watanabe@necel.com

Organizational Sponsors:
            Japan Electronics and Information Technology Industries
               Association (JEITA)
            EIA IBIS Open Forum

Co-sponsors (in alphabetical order):
            ATE Service Corporation (Sigrity)
            Cadence Design Systems
            Cybernet Systems (formerly KAW)
            Mentor Graphics
            Synopsys

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        I B I S  S U M M I T  M E E T I N G  A G E N D A

8:30    REFRESHMENTS & SIGN IN

9:00    Introductions and Program Overview
        - Welcome, Takeshi Watanabe, (NEC Electronics, Japan)
        - Welcome to Summit, Michael Mirmak (Intel Corporation, USA)

9:15    JEITA EDA - WG Activity
        Takeshi Watanabe (NEC Electronics, Japan)

9:45    The Direction of IBIS as a Standard
        Michael Mirmak (Intel Corporation, USA)

10:00   System-Level Timing Closure Using IBIS Models
        Barry Katz (Signal Integrity Software (SiSoft), USA)

10:30   BREAK (Refreshments)

10:45   IBIS 4.2 and VHDL-AMS for Serdes and DDR2 Analysis
        Ian Dodd and Gary Pratt (Mentor Graphics Corporation, USA)

11:15   PDA for SI Analysis in LTI Systems - A VHDL-AMS Test Case
        Arpad Muranyi and Michael Mirmak (Intel Corporation, USA)

11:45   ODT, Pre-Emphasis, and Speed
        Bob Ross (Teraspeed Consulting Group, USA)

12:00   FREE BUFFET LUNCH (Hosted by Sponsors)

12:45   Case Study: Spice Macromodeling for PCI Express Using
        IBIS 4.2
        Wang, Lance (Cadence Design Systems, USA)

13:15   Study of Interconnect Model
        Hiroaki Ikeda Japan Aviation Electronics, Japan)

13:45   System-Level SSO Simulation Techniques with Various IBIS
        Package Models
        Sam Chitwood*, Jack W.C. Lin**, and Raymond Y. Chen*
        (Sigrity, *USA and **China)

14:15   IBIS Model Engineering for SI Analysis
        Kazuhiko Kusunoki (Cybernet Systems, Japan)

14:45   CONCLUDING ITEMS, BREAK

15:00   END OF IBIS SUMMIT MEETING

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