[IBIS-Users] Ibis open drain strange behaviour

From: Roberto IZZI <roberto.izzi_at_.....>
Date: Thu Jan 11 2007 - 08:08:19 PST
Hello everybody

I 'd like to have some information about a strange behaviour of Open
drain buffer Ibis model.
I have noticed a mismatch between Transistor level and Ibis model
voltage output during a transient analysis, considering the same buffer.
In fact in presence of the same input voltage wave and for a high value 
of load resistance(for example 20Kohm)connected to power,
we can observe a delay between TL output and Ibis output. 
In the Ibis file, for Open drain, Rise and fall waves tables have been extracted 
considering the same resistance connected to Power (20Kohm).
What is the cause of this strange behaviour?

  Thanks and best regards

        Roberto Izzi
    


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Received on Thu Jan 11 08:09:17 2007

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