[IBIS-Users] Variety of Aproaches on IBIS Modeling on Differential I/O Buffers (with and without Pre-/De-Emphasis)

From: <Radovan.Vuletic_at_.....>
Date: Fri Feb 09 2007 - 08:43:58 PST
Hi experts,

for long time I was hoping that I will never have to do it, but now, with DDR4 (or NMT) knocking on the door it is finally on my schedule - IBIS models for differential I/O buffers.

I have to say that I have read all possible documents (or at least I think so) available on Internet (IBIS Summits, Macro Modeling Subcommittee, etc..), I have contacted a few people to discuss what they have actually done, I have done the "homework" by experimenting with *-AMS Macro Library (one year later, but still), and so I would like here to share with you one summary on possibilities to create either IBIS models for differential buffers (w/ or w/o pre-/de-emphasis) or to create setups for simulation of these buffer. Also, in this my "analysis", I would have some questions, so if somebody knows the answers, please just write me.

Disclaimer:
I am perfectly aware that there is a possibility that I have, perhaps,  wrote something wrong or stupid (I apologize in advance), but I am ready to take this risk, since I think that one of the purposes of this forum is discussing all possible (IBIS related) topics. Also, if I have forgotten to mention some work or author that is not done on purpose, but simply because of my limited capabilities.

Main question:
I know that it is impossible to get one general answer on this (but still, therefore I have done a whole analysis): What is mainstream solution/method - what is the setup that are most customers looking for? 
I am asking this simply, because I wouldn't like to support every possible existing setup, but just to concentrate on one or two.

In this summary, I have tried to list all kind of models/methods, starting with (according to me) most simple and than slowly increasing complexity - also I would like to distinguish between models of Differential buffers without Pre/De-emphasis and models of Differential buffers with Pre/De-emphasis.

Differential Buffers w/o Pre/De-emphasis 

1. "Traditional" IBIS modeling - treats differential buffers as two independent [Model]s driven by a stimulus and its complement 
Method described (for example) by:
- http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf
- http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf

Advantages:
- simple setup and usage

Disadvantages:
- not describing the coupling effects between pads
- causes DC shifts in the signal level


2. Method described by
- A. Tambone (Semiconductor Business News 2000) - no link found 
- http://www.vhdl.org/pub/ibis/summits/mar01/hegazy.pdf.Z
- http://www.vhdl.org/pub/ibis/summits/jun02/burns.pdf
- http://www.vhdl.org/pub/ibis/summits/mar03/sporrer.pdf

Advantages:
- relatively "smooth" and easy flow for understanding of IBIS extraction;
- relatively easy to adapt existing s2ibis2 or s2ibis3 flow;

Disadvantages:
- LVDS IBIS models are accurate only when same VDDQ model was generated with is used - Changing VDDQ leads to very inaccurate results;
- LVDS IBIS models assume constant Vcm - Must generate multiple models for different values of vcm to obtain consistent accuracy driving different loads and topologies;
- Device asymmetry will affect accuracy of model - Model generated for both pads assumes perfect driver symmetry - Etch lengths of nets in differential pair matched;

3. Improved IBIS modeling approach (using only v3.2 keywords)
Method described by:
- http://www.vhdl.org/pub/ibis/summits/oct02/muranyi.pdf
- http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf
- http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf

Advantages:
- describes DC currents of a differential buffer completely and accurately
- DC levels of the signals are correct under all loading conditions

Disadvantages:
- pretty complicated procedure for extraction of model (at least for me)
- relatively big effort needed to automate the procedure
- need to make some guesses for picking up the 'best" value for C_comp

Questions:
Q1:
on Page 38 and Page 39, in section "4.6.3 Separating the On-die Termination I-V Tables" of IBIS Modeling Cookbook (IBIS Open Forum) - above mentioned http://www.vhdl.org/pub/ibis/cookbook/cookbook-v4.pdf -is written:

"The procedure for this is similar to the corresponding subtraction procedure used for single-ended drivers. The
I-V characteristics of the driver must be obtained twice, once in the driving mode and once in the 3-stated (high
impedance) mode, and the 3-stated I-V table data must be substracted from the driving I-V table data. The only
added complexity in this procedure for differential drivers is that the subtraction is done after the common mode
I-V tables have been extracted from the raw I-V surface data."

On what is exactly meant by "The only
added complexity in this procedure for differential drivers is that the subtraction is done after the common mode
I-V tables have been extracted from the raw I-V surface data." . What is the difference comparing to procedures that are done with s2ibis2 or s2ibis3, since there is well done substracting of 3-stated I-V tables from driving I-V tables?

Q2:
is there some IBIS file available that is created with exactly this procedure? Can somebody send me such file?

Q3:
are there any public available tools (something like s2ibis2 or s2ibis3) that would support extraction of IBIS models described with this model?
(Hereby I don't mean on HSpice, Matlab and Pearl scripts provided in http://www.vhdl.org/pub/ibis/summits/oct03/muranyi.pdf)


Differential Buffers w/ Pre/De-emphasis 

1. "Traditional" IBIS modeling - Model the building blocks of the buffer with independent [Model]s and tell the user to wire them up
treats differential buffers as four independent [Model]s  (2 Main, 2 boosts) driven by a stimulus and its complement 

Disadvantage:
- This approach was used initially for many models but required manual editing of files and/or simulation schematics


2. [Driver Shedule] Method for Pre-emphasis Buffer modeling 

http://www.vhdl.org/pub/ibis/summits/jun01/hegazy.pdf - (basically describes 2 methods: V-I Through Transient simulation and [Driver Shedule])
http://www.vhdl.org/pub/ibis/summits/jun01/reid.pdf

Advantage (of  V-I Through Transient simulation method):
- relatively simple method

Disadvantage (of  V-I Through Transient simulation method):
- Non-monotonic wave forms (For some EDA tools)
- Single clock frequency operation (Changing the frequency needs remodeling)

Advantage (of [Driver Schedule] Method):
- Changing the frequency doesn't need remodeling
- Eliminates the need for connecting two separate [Model]s by hand in the
- Eliminates the need for manually connecting [Model]s to make a complete buffer schematics, one for the Main and one for the Boost portion of the buffer
- Fewer transistor level (SPICE) models will need to be released to customers
- Uses no more than IBIS v3.2 syntax
- Useful for tools not supporting the *-AMS extensions of IBIS - Extends the life of legacy IBIS before requiring the IBIS v4.1 language extensions
- Reasonably good correlation with transistor level model

Disadvantage (of [Driver Schedule] Method):
- Changing the frequency need changing of Rise_on, Rise_off, Fall_on and Fall_off times. Since legacy IBIS does not have provisions for clocked buffers, this model
doesn't have a clock input, consequently the delay parameter is "hard coded" and will need to be changed manually in the IBIS file for every clock frequency and
simulation corner
- The [Driver Schedule] delay parameters do not have typ., min., max. corners
 Obtaining separate [Model] data for the Main and Boost buffers may still require the editing of the SPICE netlist
- There are a few questions around proper handling of C_comp

3. IBIS modeling using v4.1 and v4.2 features (e.g. [External Circuit])

Advantage:
- flexibility (I guess so)

Disadvantage:
- not all EDA tools support all features
- relatively complicated setup

Question:
Q4:
- can somebody send me an example of IBIS model that is using v4.1 and v4.2 features for describing Differential Buffers with Pre-/De-emphasis?

4. *-AMS Buffer Models Using IBIS v3.2 Data (although it can be applied on Differential Buffers w/o Pre/De-emphasis  as well)
Method described by (and many others):
http://www.vhdl.org/pub/ibis/summits/jun03a/muranyi1.pdf
http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf
http://www.vhdl.org/pub/ibis/summits/apr04/muranyi.pdf
http://www.vhdl.org/pub/ibis/summits/oct06a/wang.pdf
http://www.vhdl.org/pub/ibis/summits/mar06/muranyi2.pdf

Advantage:
- according to my opinion absolutely the most "coolest" method (as mentioned on the beginning, I have done the homework and really experimented with Macro Model Library created by Arpad & Co. - please see my questions and comments bellow) for SI simulation
- very flexible method, gives you possibilities to do literally whatever you want (the only limitation are your EDA tools - in my case HSpice 2006.09 and it's Verilog-A interface)

Disadvantage:
- "where" is IBIS here? (not really a disadvantage, but more like a question)
- need to create IBIS models first and then to extract data in proper format (later to be read-out by Verilog-A)
- relatively high effort to create a proper setup and flow
- one needs to know (or at least understand) all :IBIS, HSpice and *-AMS - (at least in this case that wasn't my problem :-)))

Questions:
Q5:
is there a possibility to make HSpice more verbose when debugging it's Verilog-A interface? 
In sum I spent around half 0of the day just on debugging why Verilog-A "won't" compile Verilog code when including extracted IBIS data. 
Btw., please find in the attachment slightly changed Perl script  (file name: "ibis2ams.pl") with which one can REALLY do something used in conjunction with for example http://www.vhdl.org/pub/ibis/macromodel_wip/template_lib/Verilog-A_PreDe- - original script that is on http://www.vhdl.org/pub/ibis/macromodel_wip/tools/IBIS-to-AMS_conversion_tool.zip can't be  since original script generates array "Ipu_data", and pre/de-emphasis template (Verilog-A code) requires array named  "I_pu" (and other similar discrepancies). User just needs to change in the first row the path to his/her Perl executable. If IBIS model is generated with s2ibis2 user still needs to delete "S" (from pS) from generated data file.

Q6:
practical question - it seems that Verilog-A doesn't support "NA" in input array (e.g. "NA" in power or ground clamp data), although it is allowed in IBIS. Is there intention to change this in Verilog-A standard? Or at least how to handle "NA' in future?

Q7:
is it fair to say that calculation procedure (calculating/compensating of the I, V and C) used and described in "IBIS_macro_library.va" in module "IBIS_IO" is expected to be used by all other simulators - I mean, is it "The Algorithm" (with some minor changes and vendor specialties) that every tool that uses IBIS models should follow? 


Many thanks to those that have read this mail until here, I am hoping on some your feedback!


Best regards / Mit freundlichen Grüßen / S po¹tovanjem
Radovan Vuletiæ

Qimonda AG
QAG PD PDE MEM
MUC/10.2.236 AP 3
Am Campeon 1-12
D-85579 Neuebiberg

Phone:		+49 (0)89 60088 1233
Fax (PC):	+49 (0)89 60088 45 5305 

E-mail: radovan.vuletic@qimonda.com
 <<ibis2ams.pl>> 

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Received on Fri Feb 9 08:44:40 2007

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