RE: [IBIS-Users] V/T Window adjustment

Shiv,

When correlating with spice, it is almost always necessary to use two
different stimuli to the spice and IBIS buffers.  The two stimuli I use
differ in rise/fall times, voltage levels, AND initial delay.  See my
example below:

*                           V1   V2 delay       slewr slewf  pw
per
Vin_spice in_spice 0  PULSE vss vcc delay_spice 100ps 100ps  pw_spice
per_spice
Vin_ibis  in_ibis  0  PULSE 0   1   delay_ibis  1ps   1ps    pw_ibis
per_ibis

The delay_ibis parameter can be adjusted in corner cases to get the
output waveforms to overlay.  The adjustment should be directly related
to how much of the startup time you trimmed off of the curves.  The
trimmed time is not all that important, since it would normally be
"removed" by the buffer delay simulation anyways, but the trimmed time
can be documented in case it is needed in some timing budgets.  For more
info on the buffer delay I mentioned, see the IBIS reflector discussion
entitled "How can we model startup time in IBIS" from two weeks ago.

Regards,
Randy

-----Original Message-----
From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On
Behalf Of Shiv Harit MATHUR
Sent: Tuesday, May 29, 2007 10:39 PM
To: rrwolff; twesterh@sisoft.com; cary_mandel@mentor.com
Cc: ibis-users@eda.org
Subject: Re: [IBIS-Users] V/T Window adjustment

Hello,

Thanks allot for your prompt and very useful suggestions. 

As you said we can trim off V/T curves dead-times, maintaining corner
correlation intact while losing out synchronisation across corners.
Now if i do so, then how can we validate our model ??

Also, does there exist some way to add these trimmed delay values in the
model or the tool for different corners.
I think the dead-time value should be added to the internal delay value
to avoid overclocking.

Regards
Shiv Harit Mathur



rrwolff@micron.com wrote:

>Shiv,
>
>I have modeled similarly fast switching buffers by removing leading 
>"dead" time from the V-t waveforms.  I treat min, typ, and max corners 
>as independent sets of V-t curves.  Make sure to remove the same amount

>of time from all 4 min curves, typ curves, or max curves to maintain 
>the correct timing between the curves to different termination 
>voltages.  I also document in the Notes section of the model the amount

>of time I shift the typ relative to the max and the min relative to the

>max (in case someone wants to match up the spice model to the IBIS
model).
>
>You only show one set of V-t waveforms in the attached JPEG, but 
>assuming that these curves represent the earliest switch times, I would

>trim off approximately the following delay times from the three
corners:
>
>Max: 90ps
>Nom: 175ps
>Min: 350ps
>
>I suggest you submit your model to the IBIS Model Review Committee when

>you are done and ready for a final check.
>
>Regards,
>Randy
>
>Randy Wolff
>SI Modeling Manager
>Signal Integrity R&D Group
>Micron Technology, Inc. 
>
>
>-----Original Message-----
>From: owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] On 
>Behalf Of Shiv Harit MATHUR
>Sent: Tuesday, May 29, 2007 4:14 AM
>To: ibis-users@eda.org; ibis-users@eda.org
>Cc: Shiv Harit MATHUR
>Subject: [IBIS-Users] V/T Window adjustment
>
>Hello Experts,
>
>I am trying to model a buffer whose freq of operation is 1.5Ghz (time 
>period = 666ps).
>While extracting the V/T curve for the buffer we need to take up a 
>window of not less than 800ps to cover all the three waveforms. The 
>buffer delay in MAX,NOM and MIN CORNERS is 130.31ps, 228.44ps and 
>424.08ps respectively.
>
>Please find the snapshot view of the rising output waveform "TXP" of 
>the buffer in three corners, "SB" is the Input data given to the buffer

>(the
>  delay values are almost same for the falling stimuli also)
>
>Now the problem is that if I extract and dump these values in the IBIS 
>model, the model will certainly fail in the worst and typical cases as 
>the bit time is 333ps (< V/T window size). Although it will give a good

>match only if MAX corner is considered.
>
>Can anybody please suggest, what could be done for this case in order 
>to model the behaviour of the buffer correctly in all three corners ?
>
>Regards
>Shiv Harit Mathur
>STMICROELECTRONICS PVT LTD
>INDIA
>
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>
>  
>

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