Re: [IBIS-Users] Dynamic behaviour of buffer

Muniswara,

The other possible solution the obvious one - use a SPICE model for the 
buffer - which could be either a transistor model or a behavioral 
structural model using controlled sources.

The issue here is one of portability; there are a number of EDA/SI tools 
that use SPICE (or HSPICE) as their simulation engine, and could 
therefore make use of such a model.    VHDL-AMS is certainly capable of 
modeling this behavior, but there are far fewer tools that would be able 
to run the model.  If you're a semiconductor vendor producing a model 
for end-users, that's usually a consideration - you want a model that 
will run in as many tools as possible.

Wouldn't it be nice if we could run SPICE models as easily as we use 
IBIS models?  It's really not that hard. You simply need a traditional 
IBIS buffer model that also points to a corresponding SPICE model.  The 
traditional IBIS buffer model only represents a single case of output 
loading, as you pointed out.  The SPICE model works in any loading 
condition.  If a particular EDA tool can't use the SPICE model directly, 
it still has a conventional IBIS buffer model based on the specific 
loading condition.  If the EDA tool is able to use the SPICE model, then 
the user gets both the increased precision of the SPICE model and the 
benefit of the IBIS use model (graphically place the device in the 
schematic, connect it up, and simulate).
The use of the SPICE model is transparent to the user, who gets the 
benefit of SPICE modeling without any changes to the way they run their 
simulations.

I'm sure you've already guessed - but that's exactly how our software 
works, and also _why_ it works that way.  We think combining the IBIS 
use model with the enhanced precision of SPICE models makes good 
practical sense.

Todd.

Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com



Muniswara Reddy Vorugu wrote:
>
> Hi Prabhat,
>
> I have also, faced the same problem, while modeling Low-speed mode of 
> USB1.1.
>
> Tried many options of R_fixture and C_fixture, but did not find any 
> improvement.
>
>  
>
> It looks like, we should be very lucky to get proper matching using 
> the VT tables.
>
> To understand the cause of the inability of VT table methodology, look at
>
> slide4-5 of the following presentation.
>
> http://www.vhdl.org/pub/ibis/summits/jun03b/muranyi1.pdf
>
>  
>
> It looks like; AMS-VHDL is the only solution.
>
> The above presentation contains the concept of AMS-VHDL also.
>
>  
>
> Hope this helps you.
>
>  
>
> Regards,
>
> Muniswar
>
>  
>
> ------------------------------------------------------------------------
>
> *From:* owner-ibis-users@eda.org [mailto:owner-ibis-users@eda.org] *On 
> Behalf Of *Prabhat Ranjan
> *Sent:* Thursday, August 28, 2008 12:59 AM
> *To:* ibis-users@eda.org
> *Subject:* [IBIS-Users] Dynamic behaviour of buffer
>
>  
>
> Hello Experts,
>
>  
>
> I have a driver with Slope control circuit at output pin. This circuit 
> controls driver behaviour according to the Load on output pin.
>
>  
>
> IBIS model of this buffer has only R_fixture but when I am simulating 
> IBIS model with certain capacitive load then IBIS is not able to 
> produce exact SPICE behaviour.
>
>  
>
> My observation for mismatch is dynamic behavior of Slope control 
> circuit with load which I am not able to model in IBIS.
>
>  
>
> My question is how can I model the dynamic behaviour of Slope control 
> circuit in IBIS ?
>
>  
>
> Regards
>
> Prabhat
>
>
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