Re: [IBIS-Users] Dynamic behaviour of buffer

Arpad,

SPICE simulation performance varies widely depending on the complexity 
of the model.  I've seen performance ranging from less than 2 to more 
than 1000 bits/minute (and that's just with the models I've run in the 
past few months).  I don't think we're talking about simulating a SerDes 
channel here (i.e. no one was talking about simulating 100,000 bits or 
more), and I don't sense that the behavior to be represented requires an 
extracted post-layout transistor-level model.

Thus, I don't think that "having enough time for the simulations to get 
done" will be the limiting factor.

Todd.

Todd Westerhoff
VP, Software Products
SiSoft
6 Clock Tower Place, Suite 250
Maynard, MA 01754
(978) 461-0449 x24
twesterh@sisoft.com
www.sisoft.com



Muranyi, Arpad wrote:
> Prabhat,
>  
> There may be two independent reasons for your
> problem.  The capacitive loading is one, and
> I have investigated that problem some time
> ago:
>  
> http://www.vhdl.org/pub/ibis/summits/mar06/muranyi1.pdf
>  
> The other problem you may be facing is the
> slew rate control feature in your buffer.
> If this is designed with feedback from the
> output pad, traditional IBIS models are not
> going to be able to model it behaviorally.
>  
> Both of these problems could be overcome by
> using one of the *-AMS language extensions of
> IBIS, but you would have to come up with the
> algorithms for them.
>  
> As Todd pointed out, another option is to revert
> back to the SPICE model of the buffer if you have
> enough time to wait for the simulations to get
> done.  (SPICE tends to have a lot of detail and
> therefore it can be very slow).  Most EDA vendors
> I know of have support for various SPICE engines
> in their PCB tools, including ours (Mentor).  You
> do not need IBIS to bring in these SPICE models
> into these tools.
>  
> Arpad
> ===================================================
>  
>
> ------------------------------------------------------------------------
> *From:* owner-ibis-users@server.eda.org 
> [mailto:owner-ibis-users@server.eda.org] *On Behalf Of *Prabhat Ranjan
> *Sent:* Wednesday, August 27, 2008 2:29 PM
> *To:* ibis-users@server.eda.org
> *Subject:* [IBIS-Users] Dynamic behaviour of buffer
>
> Hello Experts,
>  
> I have a driver with Slope control circuit at output pin. This circuit 
> controls driver behaviour according to the Load on output pin.
>  
> IBIS model of this buffer has only R_fixture but when I am simulating 
> IBIS model with certain capacitive load then IBIS is not able to 
> produce exact SPICE behaviour.
>  
> My observation for mismatch is dynamic behavior of Slope control 
> circuit with load which I am not able to model in IBIS.
>  
> My question is how can I model the dynamic behaviour of Slope control 
> circuit in IBIS ?
>  
> Regards
> Prabhat
>
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