RE: [IBIS-Users] Timing test load

From: Muranyi, Arpad <Arpad_Muranyi_at_.....>
Date: Wed Oct 15 2008 - 07:51:40 PDT
Prabhat,
 
If that Rseries is there all the time, you
could include it in the I-V curves.
Just an idea...
 
Arpad
============================================

________________________________

From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Prabhat RANJAN
Sent: Wednesday, October 15, 2008 2:21 AM
To: twesterh@sisoft.com
Cc: ibis-users@server.eda.org; Prabhat RANJAN
Subject: Re: [IBIS-Users] Timing test load


Hello Tod,

A series resistor is used with parrallel terminated load in JEDEC SSTL_2
Class I or ClassII Output Buffers.

I think "parallel terminated loads with series resistor" should be
defined as  timing test load in IBIS models
 because this setup is also used for timing measurement of buffers.

In my case Series resistance value is 25 Ohms.


thanks n regards
Prabhat


Todd Westerhoff wrote: 

	I agree with Arpad ... with the spec as it exists today, I don't
think you can specify a series resistance in the test load.
	
	What value of Rseries are you looking to include, and what is
its purpose in the reference timing measurement?
	
	Todd.
	
	Todd Westerhoff
	VP, Software Products
	SiSoft
	6 Clock Tower Place, Suite 250
	Maynard, MA 01754
	(978) 461-0449 x24
	twesterh@sisoft.com
	www.sisoft.com
	  


	Muranyi, Arpad wrote: 

		I am not sure you can.  The keyword [Test Load] may
		let you do it with Rs_near and Rs_far, but I don't
		see a Vmeas in this keyword, and its purpose is
		slightly different (Golden Waveforms).
		 
		Arpad
		====================================================

________________________________

		From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Prabhat RANJAN
		Sent: Monday, October 13, 2008 6:59 AM
		To: ibis-users@server.eda.org
		Cc: Prabhat RANJAN
		Subject: [IBIS-Users] Timing test load
		
		
		Hello Experts,
		
		For a Output buffer IBIS model, I have following type
Timing test load setup.
		
		
		 _________
		|                   |
		|               |\ |                      Rseries
Rref
		|DRIVER|  \|---O----/\/\/\----O----/\/\/\---o Vref
		|               |  /|
|
		|               |/  |
--- Cref
		|_________ |                                 ---
	
|
	
|
		                                                   GND
		
		
		Vref, Cref and Rref keywords are existing in IBIS spec.
But how can I mention Rseries resistance as TIMING TEST LOAD in my IBIS
model?
		
		
		-- 
		
		Thanks n Regards
		Prabhat Ranjan
		
		  

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Regards
Prabhat Ranjan


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Received on Wed Oct 15 07:53:08 2008

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