RE: [IBIS-Users] How to model Flip-Chip Die IBIS model

Hi Aman,
If you are going to run the simulations than most commercial EDA tools will
probably support the mixing of SPICE and IBIS models together. But the
implementation may be difficult depending on how your EDA tool works. Most
tools by default will take the IBIS buffer component and then hook up the
correct .pkg RLC matrix structure. However in your case you want to insert a
SPICE model in between the IBIS and .pkg component if I understand you
correctly. It will probably be best if you contact your tool vendor to see
what support they have for this option. One work-around would be to use the
IBIS buffer component with no package at all, than include your SPICE model,
and then hook up the .pkg component maybe by using a Terminator model or
dummy driver. Again the implementation will really depend on the options
allowed by your tool vendor. You could always take the .pkg data out of the
IBIS file and re-format into a separate SPICE model as well. Finally you may
be able to model the on-die interconnect using the IBIS EBD or ICM format. 

Hope this helps,

Timothy Coyle
President
Signal Consulting Group LLC
405 Western Ave #430 
South Portland, ME  04106
Tel:  617.297.2566
Email: tim.coyle@siconsultant.com
Web:   http://www.siconsultant.com
SharkSim - IBIS Modeling Made Easy


-----Original Message-----
From: owner-ibis-users@server.eda.org
[mailto:owner-ibis-users@server.eda.org] On Behalf Of Aman MALHOTRA
Sent: Wednesday, July 08, 2009 8:07 AM
To: ibis-users@server.eda.org; ibis-info@server.eda.org
Subject: [IBIS-Users] How to model Flip-Chip Die IBIS model

Hello All,

I need help to model a Flip-Chip die.

I have a .pkg file which models the RLC from the die bump to the BGA 
balls. I also have the IBIS models of individual IO?s.

On the die there is a connection from the IO to the Die Bump 
for which I have the Spice netlist.

1) Is there a way to plug this spice netlist between the IO and 
the die bump?

2) If not how do we consider the parasitics of this interconnect 
on the Chip Level IBIS model? It cannot be done inside the .pkg file
as it contains the impedance values which are frequency dependent.

3) Can we use a spice file instead of .pkg file for package 
modeling. If yes how?

Any help is highly appreciated.

Regards

Aman


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