[IBIS-Users] Asian IBIS Summit (Taiwan) - Fifth Announcement

From: Bob Ross <bob@teraspeed.com>
Date: Fri Oct 22 2010 - 12:33:34 PDT

To All:

The IBIS Open Forum is holding an Asian IBIS Summit Meeting on
Friday, November 12, 2010, in Taipei, Taiwan, a major technology
center.

The event is being held at the Sherwood Hotel. Co-sponsors are
listed below. We are planning for a large number of attendees
including several IBIS experts from the USA.

The titles of 9 presentations are shown below. Several of these
presentations will be given at the other Asian Summits.

Please register to attend.

Two other Asian IBIS Summit meetings are being held in November:

   Shenzhen, P.R. China, Tuesday November 9, Four Points Hotel
   Tokyo, Japan, Monday, November 15, JEITA headquarters

Bob Ross
Teraspeed Consulting Group

Polin Chi
Sigrity

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                          ASIAN IBIS SUMMIT (TAIWAN)
                        FIFTH CALL FOR PARTICIPATION
-----------------------------------------------------------------------

             A S I A N I B I S S U M M I T ( T A I W A N )

Time/Date: Friday, November 12, 2010, 8:00 to 16:30 (date correction)
             Meeting starts at 8:30 AM

Location: Sherwood Hotel
             11 Min Sheng E Road, Sec. 3
             Taipei, Taiwan

Rooms: Ballroom I and II

Content: Presentations and Discussions

Purpose: Solicit and exchange IBIS and interconnect model related
             information and ideas.

Co-sponsors (in alphabetical order):
             Agilent Technologies
             Avant Technology (IO Methodology)
             Foxconn
             ICT-Lanto
             Intel Corporation
             Sigrity
             Synopsys

Cost: FREE, including refreshments and buffet lunch

Vendors: Some vendors will have information tables outside
             the meeting room

             Contact us for details regarding sponsorship.

BACKGROUND

    We have held many successful Summit meetings across Asia in previous years.
    This year we are adding a meeting in Taipei where many national and
    international high technology companies have operations. Presentations
    from past events are available at our Summit archive:

      http://www.eda.org/pub/ibis/summits/

    Our objective is to reach out internationally to communicate with
    the local experts and to learn of regional concerns.

CONFERENCE LANGUAGE

    The conference language is English, but we will plan for technical
    translations in English and Chinese. So presenters can optionally
    deliver in Chinese as long as an English version of the material is
    available.

IBIS SUMMIT

    This meeting will be conducted as a formal IBIS Summit Meeting.
    Presentations will be archived in an electronic format on our
    Summits site, and minutes of the meeting will be issued. However,
    no formal decisions requiring votes will be planned.

CALL FOR PARTICIPANTS

    People involved in IBIS and interconnect model development, EDA
    tool development, and digital circuit design are invited to
    participate in the Summit meeting. If you plan to participate,
    please register using the information below (in English):

      Name:
      E-mail address:

      Company:
      Top-level Web Link:

      Country:
      Telephone:

      Comments:

    Send to BOTH:

      Bob Ross, Teraspeed Consulting Group bob@teraspeed.com
      Polin Chi, Sigrity polinchi@sigrity.com

    SIGNUP DEADLINE: November 4, 2010

AGENDA

    8:00 - 8:30 Vendor table setup and tables
    8:00 - 8:30 Sign in
    8:30 - 12:00 Presentations
    12:00 - 13:30 Free buffet lunch, vendor tables
    13:30 - 16:30 Presentations

    The specific agenda is being developed. The presentations cover
    a range of topics from user experiences, IBIS clarifications, and
    future technical directions in IBIS.

    Program Titles:

    Intel Corporation
      Introducing IBIS
    IO Methodology:
      Point Reduction Method for IBIS Curves
    Sigrity
      IBIS for SSO Analysis
    Micron Technology:
      Correlating C_pin Capacitance with Measurements
    Foxconn
      Enforced Passivity of S-Parameter Sampled Frequency Data
    Agilent Technologies:
      Automated AMI Model Generation & Validation
    Flextronics and Cadence Design Systems:
      Extending/Leveraging IBIS Constructs to Model High-Speed I/Os
      and Packages using AMI, Spice, and S-Parameters
    Intel Corporation:
      IBIS-ISS: What Is It and What It Means to You
    Cadence Design Systems, Sigrity, and Fujitsu VLSI Limited:
      Model Connection Protocol Extensions for Mixed Signal SiP

LIST OF NEARBY HOTELS AND TRAVEL RULES

    Hotels in all price ranges can be found through internet searches.

-----------------------------------------------------------------

-- 
Bob Ross
Teraspeed Consulting Group LLC     Teraspeed Labs
121 North River Drive              13610 SW Harness Lane
Narragansett, RI 02882             Beaverton, OR 97008
401-284-1827                       503-430-1065
http://www.teraspeed.com           503-246-8048 Direct
bob@teraspeed.com
Teraspeed is a registered service mark of Teraspeed Consulting Group LLC
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Received on Fri Oct 22 12:33:31 2010

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