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                    BUFFER ISSUE RESOLUTION DOCUMENT (BIRD)

BIRD ID#:       91.1
ISSUE TITLE:    Multi-lingual Logic States Clarification
REQUESTOR:      Ian Dodd and John Angulo, Mentor Graphics Corp.
DATE SUBMITTED: October 4, 2004
DATE REVISED:                       
DATE ACCEPTED BY IBIS OPEN FORUM: PENDING

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STATEMENT OF THE ISSUE:

Descriptions of the D_to_A and A_to_D subparameters under [External Model]
and [External Circuit] keywords mention the allowed logic states for the 
D_receive, D_drive, D_enable and D_switch ports.  However, the existing text
does not refer to definitions of the allowed states in VHDL-AMS or 
Verilog-AMS specification documents, and does not discuss the allowed states 
outside of D_to_A and A_to_D subparameters.

The text also omits any required types of either digital or analog ports in
the AMS model.

This BIRD addresses these omissions.

BIRD 91.1:
Choice of words improved in the paragraphs specifying restrictions on port types 
and values.

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STATEMENT OF THE RESOLVED SPECIFICATIONS:

In Section 6b, under LANGUAGES SUPPORTED, replace the paragraph:

| In addition the "IEEE Standard Multivalue Logic System for VHDL Model
| Interoperability (Std_logic_1164)" designated IEEE Std. 1164-1993 is
| required to promote common digital data types.  
| 

with this paragraph:

| In addition the "IEEE Standard Multivalue Logic System for VHDL Model
| Interoperability (Std_logic_1164)", designated IEEE Std. 1164-1993, is
| required to promote common digital data types for IBIS files referencing
| VHDL-AMS.  Also, the Accellera Verilog-AMS Language Reference Manual 
| Version 2.2 is required to promote common digital data types for IBIS 
| files referencing Verilog-AMS.

In Section 6b, under the [External Model] keyword, add the following 
paragraphs after paragraph 3 of the "Ports" subsection:

|* Ports must follow certain constraints on type and state when the Language 
|* subparameter specifies VHDL-AMS or Verilog-AMS.  In VHDL-AMS models, analog 
| ports must have type "electrical".  Digital ports must have type "std_logic" 
| as defined in IEEE Standard Multivalue Logic System for VHDL Model 
| Interoperability (Std_logic_1164).  In Verilog-AMS models, analog ports must 
| be of discipline "electrical" or a subdiscipline thereof.  Digital ports must 
| be of discipline "logic" as defined in the Accellera Verilog-AMS Language 
| Reference Manual Version 2.2 and be constrained to states as defined in 
| IEEE Std. 1164-1993.
|
|* The digital ports delivering signals to the AMS model, D_drive, D_enable, and 
|* D_switch must be limited to the '1' or '0' states for VHDL-AMS, or, 
|* equivalently, to the 1 or 0 states for Verilog-AMS.  The D_receive digital 
|* port may have only the '1', '0', or 'X' states in VHDL-AMS, or, equivalently, 
|* the 1, 0, or X states in Verilog-AMS.

In Section 6b, under the [External Circuit] keyword, add the following
paragraphs after paragraph 4 of the "Ports" subsection:

|* Ports must follow certain constraints on type and state when the Language 
|* subparameter specifies VHDL-AMS or Verilog-AMS.  In VHDL-AMS models, analog 
| ports must have type "electrical".  Digital ports must have type "std_logic" 
| as defined in IEEE Standard Multivalue Logic System for VHDL Model 
| Interoperability (Std_logic_1164).  In Verilog-AMS models, analog ports must 
| be of discipline "electrical" or a subdiscipline thereof.  Digital ports must 
| be of discipline "logic" as defined in the Accellera Verilog-AMS Language 
| Reference Manual Version 2.2 and be constrained to states as defined in 
| IEEE Std. 1164-1993.
|
|* The digital ports delivering signals to the AMS model, D_drive, D_enable, and 
|* D_switch, must be limited to the '1' or '0' states for VHDL-AMS, or, 
|* equivalently, to the 1 or 0 states for Verilog-AMS.  The D_receive digital 
|* port may only have the '1', '0', or 'X' states in VHDL-AMS, or, equivalently, 
|* the 1, 0, or X states in Verilog-AMS.  All digital ports other than the 
|* foregoing predefined ports may use any of the logic states allowed by IEEE 
|* Std. 1164-1993.

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ANALYSIS PATH/DATA THAT LED TO SPECIFICATION

The present specification discusses the meaning of ports within the 
[External Model] and [External Circuit] keywords, but does not specify how they
must be defined in the underlying VHDL-AMS or Verilog-AMS languages to ensure
usability by EDA tools.  The allowed values of digital ports also must be 
defined so that tools may use them reliably.

BIRD 91.1:
Choice of words improved in the paragraphs specifying restrictions on port types 
and values.
               
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ANY OTHER BACKGROUND INFORMATION:


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