****************************************************************************** ****************************************************************************** BIRD ID#: 94 ISSUE TITLE: Clarifications on [Diff Pin] Parameters REQUESTER: Arpad Muranyi, Intel Corp. DATE SUBMITTED: December 8, 2004 DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: There are a number of issues related to the [Diff Pin] keyword in the IBIS specification. List of issues: 1) The statement: "The third column, vdiff, contains the specified output and differential threshold voltage between pins if the pins are Input or I/O model types" The problem with this statement is that, contrary to what it says, vdiff has nothing to do with outputs. 2a) The statement: "If vdiff is not defined ... vdiff is set to the default value of 200 mV" directly contradicts the statement: "If "NA" is entered in the vdiff, tdelay_typ, or tdelay_min columns, its entry is interpreted as 0 V or 0 ns", since the only way vdiff can be "not defined" if its value contains an "NA". 2b) The statement: "If a pin is a differential input pin, the differential input threshold (vdiff) overrides and supersedes the need for Vinh and Vinl" only talks about "input" pins, while this rule is valid for all other model types which have an input, such as an I/O. Also, strictly speaking there is no such thing as "a differential ... pin" (in singular). 3a) Except for the [External Model] keyword, the specification doesn't spell out any requirements about what [Model] names and model types are allowed on the [Pin] list for those pins which are associated by the [Diff Pin] keyword as a differential pair. Consequently, highly questionable and unlikely differential pairs can be created if, for example, one [Model] of the pair is an input type and the other an output type. 3b) Under the [External Model] keyword, the sentence: "The models referenced by each pin listed under [Diff Pin] MUST be the same" does not state it clearly that it is the name of the [Model] or [Model Selector] which must match. Also, when there are multiple entires under a [Diff Pin] keyword, this sentence can easily be misinterpreted to imply that the above rule must be enforced for all entries, while the intention for this rule is per entry (line) only. 3c) There is no mention in the specification how the case should be handled when there are [Model Selector] names on the pins which are associated by the [Diff Pin] keyword as a differential pair. 3d) The specification doesn't prohibit the combination of a [Model] name with a [Model Selector] name on those pins which are associated as a differential pair by the [Diff Pin] keyword. 4) The following statement has several problems: "If vdiff is not defined for a pin that is defined as requiring a Vinh by its [Model] type, vdiff is set to the default value of 200 mV" 4a) Vinl is not mentioned, yet Vinh and Vinl are usually always used together. 4b) Vinh and Vinl are not required by the specification even for buffers which have receivers in them. Default values of 0.8 V and 2.0 V are defined by the specification for the case when Vinh and Vinl are missing even if they would be needed according to the model type. 4c) The statement implies that the parser and/or simulators are expected to look inside the [Model]s which are being associated as a differential pair to find out what the model type is in order to decide whether vdiff should get a 200 mV default value in case the entry for it is "NA". Given problem #3 above, this check may return erroneous or conflicting results if the model types of the two [Model]s are not the same. 4d) The specification doesn't mention whether the values of the [Diff Pin] parameters ("NA" or number) have an implied indication for the model type, and whether this meaning has to correspond to the model type of the [Model]s referenced through the [Pin] list. 5) No meaningful error checking can be done on the entries of [Diff Pin]. This is due to the fact that the specification defines default values for vdiff and the time delay parameters in case they contain "NA". As a result, no matter what values are present in the [Diff Pin] parameter list, the model type in the [Model]s are the determining factor for how a differential pair is simulated. For one, based on item #3 above, this can be erroneous, but it may also conflict with the intentions implied by the choise of parameters used with the [Diff Pin] keyword. These default value assumptions allow a simulator to complete the simulations successfully without any errors or warnings and produce seemingly correct results without checking for any potential mistakes in the IBIS file. While this may be desirable from the perspective that simlations will be always successful, it is undesirable because serious mistakes can go undetected. 6) The assignment of default values to vdiff and the time delay parameters when their entry is "NA" conflicts with the meaning of "NA" in the [Driver Schedule] keyword, where it has a meaning of "Not Available" i.e. doesn't exist. "NA" should have the same interpretation in the entire specification, regardless of which keyword it is used for. Additionally, if the meaning of "NA" was the same for [Diff Pin] (i.e. "not available"), the parser and simulators could use these parameters for determining whether the differential pair is a receiver, driver, or I/O type. If the result of this check is in conflict with the model type found in the [Model]s, warning or error messages could be generated. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Original [Diff Pin] section: |============================================================================= | Keyword: [Diff Pin] | Required: No | Description: Associates differential pins, their differential threshold | voltages, and differential timing delays. | Sub-Params: inv_pin, vdiff, tdelay_typ, tdelay_min, tdelay_max | Usage Rules: Enter only differential pin pairs. The first column, [Diff | Pin], contains a non-inverting pin name. The second column, | inv_pin, contains the corresponding inverting pin name for | I/O output. Each pin name must match the pin names declared | previously in the [Pin] section of the IBIS file. The third | column, vdiff, contains the specified output and differential | threshold voltage between pins if the pins are Input or I/O | model types. For output only differential pins, the vdiff | entry is 0 V. The fourth, fifth, and sixth columns, | tdelay_typ, tdelay_min, and tdelay_max, contain launch delays | of the non-inverting pins relative to the inverting pins. The | values can be of either polarity. | | If a pin is a differential input pin, the differential input | threshold (vdiff) overrides and supersedes the need for Vinh | and Vinl. | | If vdiff is not defined for a pin that is defined as requiring | a Vinh by its [Model] type, vdiff is set to the default value | of 200 mV. | | Other Notes: The output pin polarity specification in the table overrides | the [Model] Polarity specification such that the pin in the | [Diff Pin] column is Non-Inverting and the pin in the inv_pin | column is Inverting. This convention enables one [Model] to | be used for both pins. | | The column length limits are: | [Diff Pin] 5 characters max | inv_pin 5 characters max | vdiff 9 characters max | tdelay_typ 9 characters max | tdelay_min 9 characters max | tdelay_max 9 characters max | | Each line must contain either four or six columns. If "NA" is | entered in the vdiff, tdelay_typ, or tdelay_min columns, its | entry is interpreted as 0 V or 0 ns. If "NA" appears in the | tdelay_max column, its value is interpreted as the tdelay_typ | value. When using six columns, the headers tdelay_min and | tdelay_max must be listed. Entries for the tdelay_min column | are based on minimum magnitudes; and tdelay_max column, | maximum magnitudes. One entry of vdiff, regardless of its | polarity, is used for difference magnitudes. |----------------------------------------------------------------------------- [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | 3 4 150mV -1ns 0ns -2ns | Input or I/O pair 7 8 0V 1ns NA NA | Output* pin pair 9 10 NA NA NA NA | Output* pin pair 16 15 200mV 1ns | Input or I/O pin pair 20 19 0V NA | Output* pin pair, tdelay = 0 22 21 NA NA | Output*, tdelay = 0 | * Could be Input or I/O with vdiff = 0 | |============================================================================= The proposed changes are noted with a "*" character at the beginning of the lines. The numbers on the left of the indented text indicate which issue the changes are addressing. |============================================================================= | Keyword: [Diff Pin] | Required: No |*Description: Associates differential pins and defines their differential |* receiver threshold voltage and differential driver timing |* delays. | Sub-Params: inv_pin, vdiff, tdelay_typ, tdelay_min, tdelay_max | Usage Rules: Enter only differential pin pairs. The first column, [Diff | Pin], contains a non-inverting pin name. The second column, | inv_pin, contains the corresponding inverting pin name for | I/O output. Each pin name must match the pin names declared |* 3a - 3d previously in the [Pin] section of the IBIS file. The model |* 3a - 3d names or [Model Selector] names referenced by the pins listed |* 3a - 3d in an entry of the [Diff Pin] MUST be the same. The third |* 1 column, vdiff, contains the specified differential receiver |* 1 threshold voltage between the inverting and non-inverting |* 1 inputs if the differential pair is or has a receiver (model |* 1 types Input, I/O, etc.). For differential pairs which do |* 4d, 5, 6 not have a receiver (model types Output, Open_drain, etc.), |* 4d, 5, 6 the vdiff entry must be "NA", otherwise it must contain a |* 4d, 5, 6 numerical value. |* |* 2b If vdiff contains a numerical entry, it overrides and |* 2b supersedes the need for Vinh and Vinl in the corresponding |* 2b [Model]s. |* |* 2a (removed paragraph) |* |* The fourth, fifth, and sixth columns, tdelay_typ, tdelay_min, |* and tdelay_max, contain launch delays of the non-inverting |* pins relative to the inverting pins if the differential pair |* is or has a driver (model types Ouput, I/O, etc.). For |* these model types, at least the tdelay_typ parameter must |* 4d, 5, 6 contain a numerical value. For differential pairs which do |* 4d, 5, 6 not have a driver (model types Input, Input_ECL), the |* 4d, 5, 6 tdelay_typ, tdelay_min, and tdelay_max entries must be "NA". |* |* All of the numerical entries may be a positive, zero, or |* negative number. | | Other Notes: The output pin polarity specification in the table overrides | the [Model] Polarity specification such that the pin in the | [Diff Pin] column is Non-Inverting and the pin in the inv_pin | column is Inverting. This convention enables one [Model] to | be used for both pins. | | The column length limits are: | [Diff Pin] 5 characters max | inv_pin 5 characters max | vdiff 9 characters max | tdelay_typ 9 characters max | tdelay_min 9 characters max | tdelay_max 9 characters max | | Each line must contain either four or six columns. If only |* 4d, 5, 6 four columns are present, or "NA" is entered in the |* 4d, 5, 6 tdelay_min or tdelay_max columns, their entry is interpreted |* 4d, 5, 6 as the tdelay_typ value. | When using six columns, the headers tdelay_min and | tdelay_max must be listed. Entries for the tdelay_min column | are based on minimum magnitudes; and tdelay_max column, | maximum magnitudes. One entry of vdiff, regardless of its | polarity, is used for difference magnitudes. |----------------------------------------------------------------------------- [Diff Pin] inv_pin vdiff tdelay_typ tdelay_min tdelay_max | * 3 4 150mV -1ns 0ns -2ns | I/O pair * 5 6 0V 1ns NA NA | I/O pair * 8 7 NA 1ns NA NA | Output pair * 9 10 10mV NA NA NA | Input pair *12 11 NA NA NA NA | Illegal combination *13 14 NA NA 0ns -2ns | Illegal combination *16 15 200mV 1ns | I/O pair *17 18 NA 1ns | Output pair *20 19 0V NA | Input pair *22 21 NA NA | Illegal combination | |============================================================================= In addition, the sentence below Fig 10 in the Usage Rules section of the [External Model] and [End External Model]: | ... The models referenced by each pin listed | under [Diff Pin] MUST be the same. should be replaced by: |* ... The [Model] names or [Model Selector] |* names referenced by the pins listed in an entry of the |* [Diff Pin] MUST be the same. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION The above proposal is a result of careful consideration of the various rules and relationships in the existing IBIS v4.1 specification. Most of the changes are about careful selection of words to avoid any ambiguities and/or contradictions. The requirement for matching the [Model] or [Model Selector] names in the proposed text above is arguable because a less strict rule of having to match the model type only would achieve similar results. However, if only the model type would be required to match, the parser or simulator would have to look inside the [Model]s to find out their model types is in order to issue any error or warning messages. Further, this less strict rule would also allow two different [Model Selector] names on differential pin pairs, which would create further complications in the simulator's [Model Selector] GUI and the related algorithms which would check whether the user selected compatible model types. On the other hand, the proposed rule of having to match the [Model] or [Model Selector] names excludes the possibility of associating two slightly different [Model]s (of the same model type) for the purpose of describing assymmetric buffer behaviors. This compromize, however, can be overcome by using the Verilog-AMS or VHDL-AMS language extensions for modeling such buffer behaviors. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: None. ******************************************************************************