****************************************************************************** ****************************************************************************** BIRD ID#: 100 ISSUE TITLE: Allow Analog-Only *-AMS Model Terminals REQUESTER: Ian Dodd, Mentor Graphics; Arpad Muranyi, Intel Corporation DATE SUBMITTED: November 10, 2005 DATE REVISED: DATE ACCEPTED BY IBIS OPEN FORUM: PENDING ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: The IBIS specification currently assumes that the signal ports of [External Model]s and [External Circuit]s are purely digital when using the *-AMS modeling languages, and a special syntax using A/D and D/A converters is required when using (analog) SPICE models. There are situations in which it may be desirable to have the capability of defining purely analog terminals in *-AMS models to be used with IBIS through the [External Model] and [External Circuit] keywords. This BIRD describes a change to the IBIS specification though which the referencing of *-AMS models containing only analog terminals is allowed. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: The Language subparameter of the [External Model] and [External Circuit] keywords shall have two additional options, namely "VHDL-A(MS)" and "Verilog-A(MS)", in which the parentheses indicates that the model uses only analog terminals. When such references to the *-AMS languages are made in [External Model]s and [External Circuit]s, the requirements of using the A_to_D and D_to_A converters with SPICE models shall apply to the *-AMS models as well. Change the following section under the [External Model] and [External Circuit] keyword descriptions: | Language: | | Accepts "SPICE", "VHDL-AMS", or "Verilog-AMS" as arguments. | The Language subparameter is required and must appear only | once. to: | Language: | | Accepts "SPICE", "VHDL-AMS", "Verilog-AMS", "VHDL-A(MS)" | and "Verilog-A(MS)" as arguments. The Language subparameter | is required and must appear only once. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION Additional detail and/or specification changes may be required to make the BIRD fully compatible with the features and syntax of Section 6b. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: ******************************************************************************