Subject:
Third Comment Set on IBIS 4.2 WIP


Please, somebody stop me...  :)

In all seriousness, this is the third and hopefully final separate list
of IBIS 4.2 WIP issues.

Less Serious
1) Section 2: missing quotation marks at the end of ver4_1.ibs and
ver4_2.ibs

Fixed.

2) Section 5: [Manufacturer] uses the phrase "the component's
manufacture" rather than "the component's manufacturer."

Fixed.

3) Section 5: [Pin Mapping] uses the phrase [Rpower] but has an opening
bracket missing

Fixed.

4) Section 6: under [Model Spec], Usage Rules contains the meaningless
phrase "it is related to the Voltage Range settings."

No Change Yet, need to consider this.

5) Section 6a, just under Fig. 12, an example is given showing
"Model_A," "Model_B" and so on.  Unfortunately, the in-line comments
refer to "A" and "B" rather than "Model_A," etc.

No Change Yet.  I agree, but this is a formating issue.  We could
  revert back to "A", "B", etc and change the diagrams or carefully
  update this area.

6) Section 7: under RLC Matrix Notes, the phrase "1amp/sec" is used
without a required space per IEEE.  Also, electrical engineering
notation is erroneously referred to as "metric."

Spacing Fixed
No Change on metric yet, but should be fixed.  suffix/muliplier notation?


More Serious
1) Section 5, under [Pin], the phrase "the default packaging values must
be used" appears, but what "default" references is never described.

No Change Yet.  Old, and I believe the reference was to [Package]
  which provided the "defaults" if entries were not given under [Pin]


2) Section 6, [Model] isn't technically required ("Required: Yes") -- I
can legally create a POWER and GND only [Pin] list and IBIS file.

No Change Yet - Check out other IBIS stuff.  You are probably right
  but Required sometimes allows for exceptions is has implied
  context assumptions.


3) Section 6, under [Model] C_comp is erroneously described as "die
capacitance" rather than "buffer capacitance" (I know this is a
frequency complaint of mine)

No Change.  Have to see the impact.  This could be used in many
  documents and locations.


4) Section 6a, under OVERVIEW, we erroneously state that [Ramp] can be
replaced.

No Change Yet.  Really meant override the [Ramp] contents.  This is
  still true, but the Ramp is retained, but its V-T information (as
  expressed as dV/dt is not used for simulation (only for EDA tools
  to estimate the separate timing simulation duration.  However ...

5) Section 6a, under Figure 7, is A_gcref permitted on both sides of the
[External Model]?

No Change Yet.  Diagram A_to_D and D_to_A can have internal
  nodes (A_myref) or the predefinded nodes.  So the left-hand
  context is for the A_to_D and D_to_A.  However, this is confusing
  and may be misleading.


6) Section 6a, under [External Circuit], the first paragraph of "Ports"
talks about [External Model] instead of [External Circuit].

Fixed.

Hopefully that's it.

- MM