(Unofficial) IBIS Version 7.0 Expanded Tree
                 Bob Ross (Teraspeed Consulting Group)
               July 25, 2006, Updated September 14, 2007, September 16, 2013, September 15, 2015, July 27, 2016,
               July 18, 2018, March 15, 2019, May 19, 2019, May 29, 2019, July 31, 2019, August 2, 2019
                           
Prior Contributers:
  Michael Mirmak (Intel Corporation)
  Bob Ross (while at Mentor Graphics, Teraspeed Labs)
  Atsushi Ogawa (NEC) - Original suggestion

Key:

  (2.1) Additions from Versions beyond basic Version 1.1:
  (3.2)   Unmarked keywords at keyword anchor level
  (4.2)   Unmarked subparameters, enumerations at level above
            or keyword anchor level
  (5.1)   Unmarked subparameters, enumerations at level above
            or keyword anchor level
  (6.0)   Unmarked subparameters, enumerations at level above
            or keyword anchor level
  (6.1)   Unmarked subparameters, enumerations at level above
            or keyword anchor level
  (7.0)   Unmarked subparameters, enumerations at level above
            or keyword anchor level


  (m)   Keyword or subparameter may occur multiple times.

  (ml)  Keyword may occur multiple times and at any location.

  *     Defined selections for keywords or subparameters are at the end.

  ----- Keywords are scoped by keyword or section above.


.ibs FILE
---------
  |-- File Header Section
  |   -------------------
  |     |-- [IBIS Ver] *
  |     |-- [Comment Char] (ml)
  |     |-- [File Name]
  |     |-- [File Rev]
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]
  |     |-- [Disclaimer]
  |     |-- [Copyright]             (2.1)
  |
  |-- [Component] (m)
  |                                 (3.2)  Si_location *, Timing_location *
  |   -----------
  |     |-- [Manufacturer]
  |     |-- [Package]                      R_pkg, L_pkg, C_pkg
  |     |-- [Pin]                          signal_name, model_name, R_pin,
  |     |                                  L_pin, C_pin
  |     |-- [Package Model]         (2.1)
  |     |   ---------------
  |     |     |-- [Alternate Package Models]      (4.2)
  |     |         --------------------------
  |     |           |-- [End Alternate Package Models]
  |     |
  |     |-- [Interconnect Model Group]           (7.0) (m)
  |     |   --------------------------
  |     |     |--[End Interconnect Model Group]           
  |     |
  |     |-- [Pin Mapping]           (2.1)  pulldown_ref, pullup_ref,
  |     |                                  gnd_clamp_ref, power_clamp_ref,
  |     |                           (4.2)  ext_ref
  |     |-- [Bus Label]             (7.0)  signal_pin
  |     |-- [Die Supply Pads]       (7.0)  signal_pin, bus_label
  |     |-- [Diff Pin]              (2.1)  inv_pin, vdiff, tdelay_typ,
  |     |                                  tdelay_min, tdelay_max
  |     |-- [Repeater Pin]          (6.0)  tx_non_inv_pin
  |     |-- [Series Pin Mapping]    (3.2)  pin_2, model_name,
  |     |                                  function_table_group
  |     |-- [Series Switch Groups]  (3.2)  On (m), Off (m)
  |     |
  |     |-- [Node Declarations]     (4.2)
  |     |     |-- [End Node Declarations]
  |     |
  |     |-- [Circuit Call] (m)      (4.2)  Signal_pin, Diff_signal_pins, 
  |     |                                  Series_pins, Port_map (m)
  |     |                           (6.0)  Converter_Parameters (m)
  |     |                           (7.0)  Parameters (m)
  |     |   --------------
  |     |     |-- [End Circuit Call]
  |     |
  |     |-- [Begin EMI Component]   (5.1)  Domain *, Cpd, C_Heatsink_gnd,
  |                                        C_Heatsink_float
  |         ---------------------
  |           |-- [Pin EMI]                domain_name, clock_div
  |           |-- [Pin Domain EMI]         percentage
  |           |-- [End EMI Component] 
  |
  |-- [Model Selector] (m)          (3.2)
  |
  |-- [Model] (m)                          Model_type *, Polarity *, Enable *,
  |                                        Vinl, Vinh, C_comp,
  |                                 (2.1)  Vmeas, Cref, Rref, Vref
  |                                 (4.2)  C_comp_pullup, C_comp_pulldown,
  |                                        C_comp_power_clamp, C_comp_gnd_clamp,
  |                                        Rref_diff, Cref_diff
  |   -------
  |     |-- [Model Spec]            (3.2)  Vinh, Vinl, Vinh+, Vinh-, Vinl+,
  |     |                                  Vinl-, S_overshoot_high,
  |     |                                  S_overshoot_low, D_overshoot_high,
  |     |                                  D_overshoot_low, D_overshoot_time,
  |     |                                  Pulse_high, Pulse_low, Pulse_time,
  |     |                                  Vmeas,
  |     |                           (4.2)  Cref, Rref, Vref, Cref_rising, 
  |     |                                  Cref_falling, Rref_rising, 
  |     |                                  Rref_falling, Vref_rising, 
  |     |                                  Vref_falling, Vmeas_rising, 
  |     |                                  Vmeas_falling, 
  |     |                                  Rref_diff, Cref_diff,
  |     |                           (5.1)  Weak_R, Weak_I, Weak_V,
  |     |                                  D_overshoot_area_h, D_overshoot_area_l,
  |     |                                  D_overshoot_ampl_h, D_overshoot_ampl_l
  |     |-- [Receiver Thresholds]   (4.2)  Vth, Vth_min, Vth_max, Vinh_ac, 
  |     |                                  Vinh_dc, Vinl_ac, Vinl_dc,
  |     |                                  Threshold_sensitivity, 
  |     |                                  Reference_supply *, Vcross_low,
  |     |                                  Vcross_high, Vdiff_ac, Vdiff_dc, 
  |     |                                  Tslew_ac, Tdiffslew_ac
  |     |-- [Add Submodel] *        (3.2)
  |     |-- [Driver Schedule]       (3.2)
  |     |-- [Temperature Range]     (2.1)
  |     |-- [Voltage Range]
  |     |-- [Pullup Reference]      (2.1)
  |     |-- [Pulldown Reference]    (2.1)
  |     |-- [POWER Clamp Reference] (2.1)
  |     |-- [GND Clamp Reference]   (2.1)
  |     |-- [External Reference]    (4.2)
  |     |-- [C Comp Corner]         (5.1)  C_comp, C_comp_pullup, C_comp_pulldown,
  |     |                                  C_comp_power_clamp, C_comp_gnd_clamp 
  |     |-- [TTgnd]                 (3.2)
  |     |-- [TTpower]               (3.2)
  |     |-- [Pulldown]
  |     |-- [Pullup]
  |     |-- [GND Clamp]
  |     |-- [POWER Clamp]
  |     |-- [ISSO PU]               (5.1)
  |     |-- [ISSO PD]               (5.1)
  |     |-- [Rgnd]                  (2.1)
  |     |-- [Rpower]                (2.1)
  |     |-- [Rac]                   (2.1)
  |     |-- [Cac]                   (2.1)
  |     |-- [On]                    (3.2)
  |     |-- [Off]                   (3.2)
  |     |-- [R Series]              (3.2)
  |     |-- [L Series]              (3.2)
  |     |-- [Rl Series]             (3.2)
  |     |-- [C Series]              (3.2)
  |     |-- [Lc Series]             (3.2)
  |     |-- [Rc Series]             (3.2)
  |     |-- [Series Current]        (3.2)
  |     |-- [Series MOSFET] (m)     (3.2)  Vds
  |     |-- [Ramp]                         dV/dt_r, dV/dt_f,
  |     |                           (2.1)  R_load
  |     |-- [Rising Waveform] (m)   (2.1)  R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |   -----------------
  |     |     |-- [Composite Current] (5.1)
  |     |
  |     |-- [Falling Waveform] (m)  (2.1)  R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |   ------------------
  |     |     |-- [Composite Current] (5.1)
  |     |
  |     |-- [Initial Delay]         (6.1)  V-T, I-T

------------------------------------------------
  |     |   OLD TREE SHOWN BELOW FOR VERSION 4.2
  |     |
  |     |-- [Test Data] (m)         (4.2)  Test_data_type *, Driver_model, 
  |     |                                  Driver_model_inv, Test_load
  |     |   -----------
  |     |     |-- [Rising Waveform Near]
  |     |     |-- [Falling Waveform Near]
  |     |     |-- [Rising Waveform Far]
  |     |     |-- [Falling Waveform Far]|
  |     |     |-- [Diff Rising Waveform Near]
  |     |     |-- [Diff Falling Waveform Near]
  |     |     |-- [Diff Rising Waveform Far]
  |     |     |-- [Diff Falling Waveform Far]
  |     |     |-- [Test Load]              Test_load_type *, C1_near, Rs_near, 
  |     |                                  Ls_near, C2_near, Rp1_near, 
  |     |                                  Rp2_near, Td, Zo, Rp1_far,
  |     |                                  Rp2_far, C2_far, Ls_far, Rs_far,
  |     |                                  C1_far, V_term1, V_term2,
  |     |                                  Receiver_model,
  |     |                                  Receiver_model_inv, R_diff_near, 
  |     |                                  R_diff_far
  |     |
  |     |   END OF OLD TREE FOR VERSION 4.2
-------------------------------------------

  |     |
  |     |-- [External Model]        (4.2)  Language *, Corner * (m), Parameters (m),
  |     |                                  Ports (m), D_to_A * (m), A_to_D * (m)
  |     |                           (6.0)  Converter_Parameters (m)
  |     |   ----------------
  |     |     |-- [End External Model]
  |     |
  |     |-- [Algorithmic Model]     (5.1)  Executable * (m)
  |     |   -------------------
  |     |                           (6.1)  Executable_Rx * (m), Executable_Tx * (m)
  |     |     |-- [End Algorithmic Model]
  |     |
  |     |-- [Begin EMI Model]       (5.1)  Model_emi_type *, Model_Domain *
  |         -----------------
  |           |-- [End EMI Model]
  |


  |       CORRECTED TREE FOR VERSION 5.1
  |
  |-- [Test Data] (m)           (4.2, 5.1) Test_data_type *, Driver_model, 
  |                                        Driver_model_inv, Test_load
  |   -----------
  |     |-- [Rising Waveform Near]
  |     |-- [Falling Waveform Near]
  |     |-- [Rising Waveform Far]
  |     |-- [Falling Waveform Far]
  |     |-- [Diff Rising Waveform Near]
  |     |-- [Diff Falling Waveform Near]
  |     |-- [Diff Rising Waveform Far]
  |     |-- [Diff Falling Waveform Far]
  |      
  |-- [Test Load] (m)           (4.2, 5.1) Test_load_type *, C1_near, Rs_near, 
  |                                        Ls_near, C2_near, Rp1_near, 
  |                                        Rp2_near, Td, Zo, Rp1_far,
  |                                        Rp2_far, C2_far, Ls_far, Rs_far,
  |                                        C1_far, V_term1, V_term2,
  |                                        Receiver_model,
  |                                        Receiver_model_inv, R_diff_near, 
  |                                        R_diff_far
  |
  |       END OF CORRECTED TREE FOR VERSION 5.1


  |
  |-- [Submodel] (m)                (3.2)  Submodel_type *
  |   ----------
  |     |-- [Submodel Spec]                V_trigger_r, V_trigger_f, Off_delay
  |     |-- [POWER Pulse Table]     
  |     |-- [GND Pulse Table]     
  |     |-- [Pulldown]
  |     |-- [Pullup]
  |     |-- [GND Clamp]
  |     |-- [POWER Clamp]
  |     |-- [Ramp]                         dV/dt_r, dV/dt_f, R_load
  |     |-- [Rising Waveform] (m)          R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |-- [Falling Waveform] (m)         R_fixture, V_fixture,
  |     |                                  V_fixture_min, V_fixture_max,
  |     |                                  C_fixture, L_fixture, R_dut, L_dut,
  |     |                                  C_dut
  |     |-- [Initial Delay]         (6.1)  V-T, I-T

  |            
  |-- [External Circuit] (m)        (4.2)  Language *, Corner * (m), Parameters (m),
  |                                        Ports *, D_to_A * (m), A_to_D * (m)
  |   ------------------
  |     |-- [End External Circuit]  
  |
  |-- [Define Package Model] (m)    (2.1)
  |   ----------------------
  |     |-- [Manufacturer]
  |     |-- [OEM]
  |     |-- [Description]
  |     |-- [Number Of Sections]
  |     |-- [Number Of Pins]
  |     |-- [Pin Numbers]                  
  |     |                           (3.2)  Len (m), L (m), C (m), R (m),
  |     |                           (3.2)  Fork (m), Endfork (m)
  |     |-- [Merged Pins]           (6.1)
  |     |-- [Model Data]
  |     |   ------------
  |     |     |-- [Resistance Matrix]      *
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [Inductance Matrix]      *
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [Capacitance Matrix]     *
  |     |     |   --------------------    
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [End Model Data]
  |     |  
  |     |-- [End Package Model]
  |
  |--[Interconnect Model Set]       (7.0) (m)
  |  ------------------------
  |     |-- [Manufacturer]
  |     |-- [Description]
  |     |-- [Interconnect Model]    (m)    Param (m) *, File_TS, File_IBIS-ISS,
  |	|				   Unused_port_termination *
  |     |				   Number_of_terminals
  |     |   --------------------
  |     |     |-- [End Interconnect Model]
  |     |
  |     |-- [End Interconnect Model Set]
  |
  |-- [End]


.pkg FILE                           (2.1)
---------
  |-- File Header Section           (2.1)             
  |   -------------------
  |     |-- [IBIS Ver] *
  |     |-- [Comment Char] (ml)
  |     |-- [File Name]
  |     |-- [File Rev]                  
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]
  |     |-- [Disclaimer]
  |     |-- [Copyright]
  |
  |-- [Define Package Model] (m)    (2.1)
  |   ----------------------
  |     |-- [Manufacturer]
  |     |-- [OEM]
  |     |-- [Description]
  |     |-- [Number Of Sections]
  |     |-- [Number Of Pins]
  |     |-- [Pin Numbers]                  
  |     |                           (3.2)  Len (m), L (m), C (m), R (m),
  |     |                           (3.2)  Fork (m), Endfork (m)
  |     |-- [Merged Pins]           (6.1)
  |     |-- [Model Data]
  |     |   ------------
  |     |     |-- [Resistance Matrix]      *
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [Inductance Matrix]      *
  |     |     |   -------------------     
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [Capacitance Matrix]     *
  |     |     |   --------------------    
  |     |     |     |-- [Bandwidth]
  |     |     |     |-- [Row] (m)
  |     |     |
  |     |     |-- [End Model Data]
  |     |  
  |     |-- [End Package Model]
  |
  |-- [End]


.ebd FILE                           (3.2)         
---------
  |-- File Header Section           (3.2)
  |   -------------------
  |     |-- [IBIS Ver] *
  |     |-- [Comment Char] (ml)               
  |     |-- [File Name]
  |     |-- [File Rev]
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]                       
  |     |-- [Disclaimer]
  |     |-- [Copyright]
  |
  |-- [Begin Board Description] (m) (3.2)
  |   -------------------------
  |     |-- [Manufacturer]
  |     |-- [Number of Pins]
  |     |-- [Pin List]                      signal_name
  |     |-- [Path Description] (m)          Len (m), L (m), C (m), R (m),
  |     |                                   Fork (m), Endfork (m), Node (m),
  |     |                                   Pin (m)
  |     |-- [Reference Designator Map]
  |     |-- [End Board Description]
  |
  |-- [End]

.ims FILE                           (7.0)         
---------
  |-- File Header Section           (7.0)
  |   -------------------
  |     |-- [IBIS Ver] *
  |     |-- [Comment Char] (ml)               
  |     |-- [File Name]
  |     |-- [File Rev]
  |     |-- [Date]
  |     |-- [Source]
  |     |-- [Notes]                       
  |     |-- [Disclaimer]
  |     |-- [Copyright]
  |
  |-- [Interconnect Model Set]       (7.0) (m)
  |   ------------------------
  |     |-- [Manufacturer]
  |     |-- [Description]
  |     |-- [Interconnect Model]    (m)    Param (m) *, File_TS, File_IBIS-ISS,
  |	|				   Unused_port_termination *
  |     |				   Number_of_terminals
  |     |   --------------------
  |     |     |-- [End Interconnect Model]
  |     |
  |     |-- [End Interconnect Model Set]
  |
  |-- [End]

----------------------------------------------------------------------------

Defined Selections (*), Reserved Words and Multipliers

  [IBIS Ver]	(.pkg)	(.ebd)	(.ims)		| enumerated
        1.0				(1.1)	| strings
        1.1
	2.0	2.0			(2.1)
	2.1	2.1
	3.0	3.0	3.0		(3.2)
	3.1	3.1	3.1
	3.2	3.2	3.2
	4.0	4.0	4.0
	4.1	4.1	4.1
	5.0	5.0	5.0		(.ami shown separately)
	5.1	5.1	5.1
	6.0	6.0	6.0		(6.0)
	6.1	6.1	6.1		(6.1)
	7.0	7.0	7.0	7.0	(7.0)

  Reserved Words
        POWER
        GND
        NC
        NA
        CIRCUITCALL     (4.2)

  Multipliers 
        M, k, m, u, n, p
        T, G, f         (2.1)

  [Add Submodel]        (3.2)  Mode column selections
        Driving
        Non-Driving
        All

  Si_location           (3.2)
        Pin
        Die

  Timing_location       (3.2)
        Pin
        Die

  Polarity              
        Non-Inverting
        Inverting

  Enable
        Active-High
        Active-Low

  Model_type
	3-state
	3-state_ECL     (3.2)
        3-state_diff    (4.2)        
	I/O
	I/O_ECL         (2.1)
	I/O_open_drain  (2.1)
	I/O_open_sink   (2.1)
	I/O_open_source (2.1)
        I/O_diff        (4.2)
	Input
	Input_ECL       (2.1)
        Input_diff      (4.2)
	Open_sink       (2.1)
	Open_drain
 	Open_source     (2.1)           
	Output
	Output_ECL      (2.1)
        Output_diff     (4.2)
	Series          (3.2)
	Series_switch   (3.2)
	Terminator      (2.1)

  Submodel_type         (3.2)
	Bus_hold
	Dynamic_clamp
        Fall_back       (4.2)

  Reference_supply      (4.2)
        Power_clamp_ref
        Gnd_clamp_ref
        Pullup_ref
        Pulldown_ref
        Ext_ref

  Test_data_type        (4.2, 5.1)
        Single_ended
        Differential

  Test_load_type        (4.2, 5.1)
        Single_ended
        Differential

  Language              (4.2)
        SPICE
        VHDL-AMS
        Verilog-AMS
        VHDL-A(MS)
        Verilog-A(MS)
        IBIS-ISS        (6.0)

  Corner, A_to_D corner_name  (4.2)
        Typ
        Min
        Max

  Corner, D_to_A corner_name  (4.2)
        Typ
        Min
        Max

  D_to_A polarity             (6.0)
        Non_Inverting
        Inverting
       
  Reserved Digital Port Names (4_2)
        D_receive
        D_drive
        D_enable
        D_switch

  Reserved Analog Port Names  (4.2)
        A_signal
        A_pos
        A_neg
        A_signal_pos
        A_signal_neg

  Reserved Analog Reference Names (4.2)
        A_pufref
        A_pdref
        A_pcref
        A_gcref
        A_extref
        A_gnd

  [Resistance Matrix], [Capacitance Matrix], [Inductance Matrix] (2.1), (7.0 names)
        Full_matrix
        Banded_matrix
        Sparse_matrix

  Domain                (5.1)
        Digital
        Analog
        Digital_analog
        
  Model_EMI_type        (5.1)
        Ferrite
        Not_a_ferrite

  Model_Domain          (5.1)
        Digital
        Analog

  Executable            (5.1)
        Platform_Compiler_Bits File_Name Parameter_File
                        (7.0) |column heading entries renamed below)
        Platform_Compiler_Bits Executable_Model_FIle AMI_Parameter_FIle

  Executable_Rx         (6.1)
        Platform_Compiler_Bits File_Name Parameter_File
                        (7.0) |column heading entries renamed below)
        Platform_Compiler_Bits Executable_Model_FIle AMI_Parameter_FIle
        
  Executable_Tx         (6.1)
        Platform_Compiler_Bits File_Name Parameter_File
                        (7.0) |column heading entries renamed below)
        Platform_Compiler_Bits Executable_Model_FIle AMI_Parameter_FIle

  [Interconnect Model] Reserved Names: (7.0)

  Param	format column	(7.0)
	Value

  Unused_port_termination  (7.0)
        Open
        Reference
        Resistance

  Terminal_types column    (7.0)
        Pin_I/O
        Pad_I/O
        Buffer_I/O
        Pin_Rail
        Pad_Rail
        Buffer_Rail
        Pullup_ref
        Pulldown_ref
        Power_clamp_ref
        Gnd_clamp_ref
        Ext_ref
        A_gnd

   Terminal_type_qualifiers column (7.0)
       pin_name
       signal_name
       bus_label
       pad_name

   Aggressor_Only column   (7.0)
       Agressor_Only