adding: Verilog-A sample buffer data/ (stored 0%)
  adding: Verilog-A sample buffer data/VT_data_ODT_Vcc_GND.dat (deflated 73%)
  adding: Verilog-A sample buffer data/LibNet.va (deflated 80%)
  adding: Verilog-A sample buffer data/disciplines.vams (deflated 79%)
  adding: Verilog-A sample buffer data/IV_data_ODT_GND.dat (deflated 68%)
  adding: Verilog-A sample buffer data/constants.vams (deflated 53%)
  adding: Verilog-A sample buffer data/VT_data_ODT_GND.dat (deflated 69%)
  adding: Verilog-A sample buffer data/test_ams.ibs (deflated 75%)
  adding: Verilog-A sample buffer data/IBIS_macro_library.va (deflated 94%)
  adding: Verilog-A sample buffer data/bblocks.va (deflated 48%)
  adding: Verilog-A sample buffer data/ibismacro.dtd.xml (deflated 60%)
  adding: Verilog-A sample buffer data/bblocks.xml (deflated 53%)
  adding: Verilog-A sample buffer data/VT_data_no_ODT.dat (deflated 69%)
  adding: Verilog-A sample buffer data/IV_data_ODT_Vcc_GND.dat (deflated 70%)
  adding: Verilog-A sample buffer data/IV_data_no_ODT.dat (deflated 68%)
  adding: Verilog-A sample buffer data/libtest.sp (deflated 68%)
  adding: Verilog-A sample buffer data/IV_data_ODT_Vcc.dat (deflated 68%)
  adding: Verilog-A sample buffer data/VT_data_ODT_Vcc.dat (deflated 68%)