Index of /adhoc/adv_tech_modeling/archive/20060228/arpadmuranyiintel/Verilog-A element library, HSPICE test/Macro_lib

 NameLast modifiedSizeDescription

 Parent Directory   -  
 IBIS_macro_library.va 2006-02-28 16:51 198K 
 No_ODT_INPUT_data.dat 2006-01-24 23:34 334  
 No_ODT_IO_OPENSINK_d..>2006-01-25 00:35 872  
 No_ODT_IO_OPENSOURCE..>2006-01-25 00:40 874  
 No_ODT_IO_data.dat 2006-01-24 23:55 1.3K 
 No_ODT_OPENSINK_data..>2006-01-25 00:29 836  
 No_ODT_OPENSOURCE_da..>2006-01-25 00:26 838  
 No_ODT_OUTPUT_data.dat 2006-01-24 23:44 1.2K 
 ODT_to_GND_INPUT_dat..>2006-01-24 23:38 334  
 ODT_to_GND_IO_data.dat 2006-01-24 23:55 1.3K 
 ODT_to_GND_OUTPUT_da..>2006-01-24 23:50 1.3K 
 ODT_to_VccGND_INPUT_..>2006-01-24 23:42 334  
 ODT_to_VccGND_IO_dat..>2006-01-24 23:55 1.4K 
 ODT_to_VccGND_OUTPUT..>2006-01-24 23:51 1.4K 
 ODT_to_Vcc_INPUT_dat..>2006-01-24 23:40 334  
 ODT_to_Vcc_IO_data.dat 2006-01-24 23:55 1.4K 
 ODT_to_Vcc_OUTPUT_da..>2006-01-24 23:50 1.4K 
 constants.vams 2005-01-20 18:02 1.3K 
 disciplines.vams 2005-01-19 18:13 5.1K