============================================================================== IBIS INTERCONNECT TASK GROUP Mailing list: ibis-interconnect@freelists.org ================================================================================ Attendees from March 19, 2025 Meeting (* means attended at least using audio) ANSYS Curtis Clark, Wei-hsing Huang, Juliano Mologni Arista Networks Jim Antonellis Broadcom James Church Intel Corp. Michael Mirmak*, Xiaoning Ye Keysight Technologies Ming Yan Marvell Steve Parker MathWorks Walter Katz* Micron Technology Justin Butterfield Siemens EDA Weston Beal, Arpad Muranyi*, Randy Wolff* Simberian Yuriy Shlepnev ST Microelectronics Aurora Sanna Synopsys Ted Mido, Edna Moreno University of Illinois Jose Schutt-Aine Zuken USA Lance Wang Michael Mirmak convened the meeting. No patents were declared. Michael raised a concern that the meeting might not have enough attendees (quorum) to conduct business. Randy Wolff confirmed that there were no specific quorum rules regarding IBIS task groups. Michael reviewed the minutes from the February 5 meeting. Arpad Muranyi moved to approve the minutes; Randy seconded. The minutes were approved without objection. Michael reviewed the minutes from the March 5 meeting. He noted that a sentence was cut off before it was completed: "He had only made a minor change" The complete sentence should have ended with "since the last draft." Arpad moved to approve the minutes with this change; Randy seconded. The minutes were approved. Michael noted that he still had an open AR to update the IBIS-ISS text with am ISSIRD to correct the character set definitions used for the files. Michael reviewed the March 12 minutes. He noted that Arpad had requested several changes, noted below, on the e-mail reflector: Change: “Arpad stated that the circuit assumptions are based on "hiding" information in the tool, not based on what GUI provides but as-is you can manually write the SPICE netlist yourself. This is like an S-element syntax.” to: “Arpad stated that the circuit connections shown are based on "hidden" information in the tool, not based on what GUI provides but as-if you wrote the SPICE netlist manually. This is like using the 2N S-element syntax.” Also, please change: “The S-element will float the circuits if you don't connect them.” to: “The S-element ports connected together will float if you don't connect them to anything else.” {MM asked about "terminals" rather than "ports"} Change: “Arpad replied that they are all internally shorted to the same node inside the box.” to: “Arpad replied that the IBIS N+1 syntax essentially shorts all reference terminals of an S-parameter block to the same node (inside the box).” Change: “Arpad replied that the two blue lines could be different in potential and you can handle this at the tool level. But if S-parameters are used, who knows? In the case of an N+1 circuit, all negative terminals are shorted.” to: “Arpad replied that if one of the two blue lines is not connected to another S-parameter block (such as an IBIS buffer rail terminal) the tool may be able to handle this correctly. But if S-parameters are used, in the case of an N+1 circuit, all negative terminals are shorted.” Arpad move to approve the minutes with these changes; Randy seconded. The minutes were approved. Michael asked about Arpad's tabled AR and suggested it be closed. Arpad agreed. Michael added a new bin list item corresponding to his March 5 AR. Michael reviewed his "three situations" slides from an earlier meeting, showing different situations where circuits (some implied to be Touchstone, others implied to be SPICE) are connected to each other. Michael talked about "loop-reduced" circuits, as in Sam Chitwood's IBIS Summit presentation. He asked whether we have a method for loop reduction. Arpad noted that broadband SPICE conversions are sometimes used; Michael agreed, pointing to the use of such models to create curve-fitted responses from S-parameter data, with error terms and a target bandwidth used to control the quality of the model's matching of frequency-domain behavior. Randy confirmed this, adding that the representation is usually pole-residue. Arpad asked whether such representations would be the same as what is shown in the three situations. Randy suggested that VSS might not be present in a circuit if there is no port for it; this is often node 0. Michael referred to modeling of the whole system, as the loop-reduced circuit equivalents become one overall system that is also terminated. He suggested thinking in terms of black boxes. Randy stated that the only thing we can do is to limit the possible connection combinations to prevent breaking of the loop; in slide 2, we could lock the buffer-to-pad, pad-to-pin connections as both SPICE or both S-parameters. Michael asked whether we can simply state that, for EMD, IBIS Interconnect, etc., any loop-reduced circuit model forces all connections to be loop-reduced. Arpad stated that this is close to the answer. The only time mixing SPICE with a VSS path and an S-parameter doesn't work is if S-parameters are used on both sides and are N+1 (all terminals are using one reference terminal). One would need an independent reference for all terminals, not necessarily ideal SPICE node 0. N+1 in this case is a loop-reduced S-parameter. Randy added that N+2 would be ideal and we should have that in IBIS Interconnect. This is like 2N but most references one or other side. Michael noted that his original "dream" was of having rules defining connections from 2N, N+1, N to other elements. Do we allow anything beyond N in EMD, IBIS Interconnect? Arpad replied that SPICE and Touchstone are totally different; S-parameters don't have Galvanic connection between ports (see two red loops). Walter Katz noted that he shared the recent e-mail thread with, and consulted, experts at MathWorks, and generated an ISS subcircuit with just ground vs. complex VSS path similar to the one shown in the slides. As long as you measure all the voltages with respect to local ground, these are equivalent and the results of circuit analysis were the same. The S-parameter knows what the reference is but the IBIS-ISS circuit does not. If you are building both models, you know the references for everything, but the EDA tool doesn't. This is also a problem for the SPIM BIRD; you can only say that the lower terminal (VSS) connects to these (other) pins. The terminals show pairs, but you don't know this. Arpad replied that you can have lots of terminals on one side, and one on the other. Walter agreed, citing an example of having 50 VDD pins but one VSS pin. SPIM constructs 1 ground terminal for every power terminal, as one way of analyzing power delivery. There could be others. Unless you know the context, connecting these two circuits is very difficult. For SI purposes, ground distribution is node 0 referencing. We never understood power delivery before in IBIS. If you are concerned about the quality of your ground interconnect, you must put constraints on how you handle both sides. Michael asked whether adding an identifier to IBIS-ISS would help. Arpad asked whether this identifier would be for which SPICE pairs are associated. Michael replied that VSS and VCC SPIM pairing already exists. Randy agreed, stating that SPIM is an S-parameter; the syntax is identifying VSS pins associated with a listed VCC, for the S-parameter. Michael suggested that our port map already satisfies our purposes for S-parameters; we need something similar for SPICE. We may have to prohibit some SPICE circuits without appropriate information in EMD, IBIS-Interconnect. Randy replied that we have that already - it's called IBIS Interconnect. Arpad noted that these structures are limited to N+1 referencing today. Randy added that it's the connection between a SPICE wrapper and IBIS Interconnect wrapper which is the problem. Walter stated that the wrapper for Touchstone files is fine; the issue is the wrapper for SPICE (R-model) for power delivery. For IBIS-ISS, we can enhance our wrapper by specifying for each terminal what its reference is; it's another item on a terminal line. Randy observed that, relative to what we have currently in EMD, IBIS Interconnect needs new definitions. Arpad asked whether we could we take care of this in EMD and IBIS Interconnect, or whether this is being done in IBIS-ISS. Randy suggested that it's all in the wrapper. Arpad noted that a wrapper could be made by a different person than who made the subcircuit. These can become separated. Randy added that he could see how we would need additional data. Walter replied that this is why the R-element uses the names of the .subckt statement vs. the order of the nodes; SPIM compliance works because of the name associations. Arpad stated that he would prefer not to use comments to indicate this kind of circuit description feature. Instead, some sort of dot feature convention or structure inside the subcircuit would be useful. Randy agreed that a completely new, different structure and not comments should be used. Walter replied that the feature syntax should be escaped comments; otherwise industry won't take it. Arpad moved to adjourn the meeting; Randy seconded. The meeting adjourned without objection. The next meeting will take place on March 26, 2025. ================================================================================ Bin List: 1) Complete port naming proposal (Katz et al) 2) Complete/revise Touchstone 3.0 draft outline (Mirmak) 3) Complete ISS-IRD 1 Draft - enable cascading of S-parameters through W-element (Mirmak) - TABLED 4) ISS-IRD ISO/IEC Tabled ARs: - Arpad to give an example of the physical connectivity needed for EMD automation.