============================================================================== IBIS INTERCONNECT TASK GROUP Mailing list: ibis-interconnect@freelists.org ================================================================================ Attendees from November 13, 2024 Meeting (* means attended at least using audio) ANSYS Curtis Clark, Juliano Mologni Arista Networks Jim Antonellis* Broadcom James Church Intel Corp. Michael Mirmak*, Xiaoning Ye Keysight Technologies Ming Yan Marvell Steve Parker MathWorks Walter Katz* Micron Technology Justin Butterfield Siemens EDA Weston Beal*, Arpad Muranyi*, Randy Wolff* Simberian Yuriy Shlepnev ST Microelectronics Aurora Sanna Synopsys Ted Mido, Edna Moreno University of Illinois Jose Schutt-Aine Zuken USA Lance Wang* Michael Mirmak called the meeting to order. No patents were declared. Michael reviewed the minutes of the November 6, 2024 meeting. Randy Wolff moved to approve the minutes; Lance Wang seconded. The minutes were approved without objection. Arpad Muranyi noted that is AR was completed, as he provided referencing examples in slides sent to the reflector. Since they were shown, he added some drawings where dummy resistors were required. Michael noted that Steven Parker had updated the IBIS website with a significant number of Task Group documents and minutes. Randy added that Steven's stated goal is to have the process more automated by end of year. Arpad reviewed his updated slides. Examples 3, 4, 10, and 11 in the IBIS specification are incorrect. Another is syntactically correct but may not be possible to create - this is an EMD with no example number on page 408. Specifically, in Example 3, terminal 3 should be changed to A_gnd. Randy noted that there is no power rail here either, just I/O, so it's OK to attach A_gnd; we also need to change the rules in the specification. Michael asked whether the rules should restrict non-physical descriptions, even if they are inconvenient (see Verilog-A/AMS, which limits frequency-domain descriptions to avoid non-physical situations). Arpad suggested that there are several ways to approach this. One could widen the specification or narrow it. In the narrow case, only A_gnd would be allowed for referencing S-parameters. In the wide case, we would allow per-interface referencing for S-parameters. We don't have this today. Arpad expressed a preference to fix the rules to prohibit the current case shown in Example 3. Ports are mysterious to many users; he himself still struggles with proper definitions. To guide the novice how not to make bad models might be useful. Michael suggested fixing the examples to be limited to using A_gnd; will this require a BIRD? Can his change become part of IBIS 8? Randy suggested he thinks this is possible. All four examples are easily fixed to use A_gnd for reference. The EMD example on page 408 is harder, as the use of a signal port for Vss is tricky. Weston Beal suggested leaving this as it is; he can work to show a relevant S-parameter-based example. Weston and Arpad will work on this example. [AR] Michael asked whether it was necessary to update the drawings with additive elements. Randy replied that this EMD example is placed between the pins and reference designator pins of an EMD model, but the drawing is for an IBIS interconnect example; the drawings do not match. Arpad agreed. Randy added that we don't have an Interconnect example exactly like this. He accepted the AR to provide one. [AR] Michael asked whether there was any value to have a drawing for the example on page 408. Weston replied that it would have value. Arpad noted his other drawings are "based on" the examples provided. Randy stated that there are no drawings in the EMD section. Arpad suggested that Figure 48 may be appropriate, but Randy replied that this was present just in the introduction and did not outline any specific examples. Michael agreed, adding that the drawing was present merely to introduce the concept of on-die pads and explicit model connections. Arpad added that it also shows on-die interconnects as separate from the package interconnects. Randy proposed not holding up IBIS 8 for new drawings. Figure 54 shows a bunch of pins on a component, with power routing; all examples in the specification are based on that picture. The picture is relevant to ISS examples; however, one has to take a leap to understand referencing for S-parameters. Arpad asked whether Figure 53 is showing buffer terminals. Randy replied that the example shows the terminals of ISS subcircuits, but then we are suddenly thrown S-parameters. It may be useful to mention Example 3 is different, with S-parameters and drawings. The same pin numbers are used. Arpad noted that the rules still allow a separate "terminal 3 " which is not tied to A_gnd. Example 15 is good. Randy noted that the example is still using an I/O declaration, ignoring power and ground. Fortunately, there is not much that has to change to make this consistent. Arpad added that Example 3 and above are showing Touchstone variants of other examples. Randy added that maybe aggressor or other features are being shown as well. Michael proposed adding a statement that Figure 53 is unrelated to these Touchstone examples. For Examples 3, 4, 10, 11, Arpad proposed moving them after the ISS examples. Randy added that the pin numbers are relevant. Weston asked whether we could have a 1:1 example. Arpad and Randy: agreed, noting that what it would take would be to include Vss *ports*; having one would be very valuable. In Example 3, terminal 3 should be A_gnd (by itself); part of the comment would therefore disappear. Randy commented that, if we are talking about rail connections to buffer I/O, EDA tools already do make those (through Pin Mapping). "Vss reference" becomes "A_gnd reference" For Example 4, Arpad asked whether signal_name reference makes A_gnd a problem here. Randy asked whether this is redundant. Arpad suggested not for buf_to_pin pad_to_pin connections, and that pad_io is unique in Example 4. Randy noted that Example 4 combines ISS and Touchstone in the same path, one pin-to-pad then pad-to-buffer. These don't work if you expect Vss to connect through the package. Weston asked whether the number of terminals is four. One needs four terminals to make the connection at the ISS side. Randy suggested this looks like one is trying to connect capacitors inside the interconnect. Weston replied that, if the capacitor is connected from the signal to pulldown_ref cap, then is it assumed to be a pad-to-buffer Vss connection? One could change the Touchstone portion to use A_gnd on terminal 3, then remove the ISS portion. Randy asked what is inside the ISS. It is not incorrect to have some terminal for ground. Walter Katz noted that having subcircuits with node Vss on the node map is dangerous. Globally, this is a local ground. For ISS, the number of terminals is 2, not 3; the circuit probably has A_gnd inside of it. There was some discussion on the proper calling and circuit definition methods for SPICE with ground and non-ideal referencing. Arpad asked whether we need subcircuit definitions to show how to do this; we don't have these in the specification currently. In Example 10, terminal 7 would change to A_gnd. Example 11 also combines Touchstone and ISS, similarly to Example 4. But here the only connections are VDD and VSS. Arpad added that, on Vladimir Dmitriev-Zdorov's slides from the IBIS Summit of February 2018, he does show compatible subcircuit and Touchstone file creation. Arpad moved to adjourn; Randy seconded. The meeting adjourned without objection. The next meeting will be held November 20, 2024. ================================================================================ Bin List: 1) Complete port naming proposal (Katz et al) 2) Complete/revise Touchstone 3.0 draft outline (Mirmak) 3) Complete ISS-IRD 1 Draft - enable cascading of S-parameters through W-element (Mirmak) - TABLED Tabled ARs: - Arpad to give an example of the physical connectivity needed for EMD automation.