***************************************************************************** ***************************************************************************** BUFFER ISSUE RESOLUTION DOCUMENT (BIRD) BIRD ID#: 89.1 ISSUE TITLE: Keyword Hierarchy Tree REQUESTOR: Michael Mirmak, Intel Corporation DATE SUBMITTED: April 5, 2004 DATE REVISED: May 11, 2004 DATE ACCEPTED BY IBIS OPEN FORUM: June 4, 2004 ***************************************************************************** ***************************************************************************** STATEMENT OF THE ISSUE: The scope of many keywords within the IBIS specification is not explicitly defined. As a result, interpretations of keyword interactions can vary among tools. Additionally, hierarchy assumptions within the golden parser may effectively create and enforce rules which the specification does not clearly establish. A hierarchical description of the scope of keywords within the IBIS specification, similar to that used for ICM, would establish more clearly the rules for keyword interaction. **************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: Changes are denoted by *. Changes in BIRD89.1 are denoted by **. The following text is to be inserted as Section 3a. |============================================================================= |============================================================================= | | Section 3a | | K E Y W O R D H I E R A R C H Y | |============================================================================= |============================================================================= | | .ibs FILE | --------- | |-- File Data Information | | ----------------- | | |-- [IBIS Ver] | | |-- [Comment Char] | | |-- [File Name] | | |-- [File Rev] | | |-- [Date] | | |-- [Source] | | |-- [Notes] | | |-- [Disclaimer] | | |-- [Copyright] | | | |-- [Component] Si_location, Timing_location | | ----------- | | |-- [Manufacturer] | | |-- [Package] R_pkg, L_pkg, C_pkg | | |-- [Pin] signal_name, model_name, R_pin, | | | L_pin, C_pin | | |-- [Package Model] | | | ---------- | | | |-- [Alternate Package Models] | | | ---------- | | | |-- [End Alternate Package Models] | | | | | |-- [Pin Mapping] pulldown_ref, pullup_ref, | | | gnd_clamp_ref, power_clamp_ref, | | | ext_ref | | |-- [Diff Pin] inv_pin, vdiff, tdelay_typ, | | | tdelay_min, tdelay_max | | |-- [Series Pin Mapping] pin_2, model_name, | | | function_table_group | | |-- [Series Switch Groups] On, Off | | | | | |-- [Node Declarations] | | | ---------- | | | |-- [End Node Declarations] | | | | | | | | |-- [Circuit Call] Signal_pin, Diff_signal_pins, | | | Series_pins, Port_map | | | ---------- | | | |-- [End Circuit Call] | | | | | |-- [Model Selector] | | | |-- [Model] Model_type, Polarity, Enable, | | Vinl, Vinh, C_comp, C_comp_pullup, | | C_comp_pulldown, C_comp_power_clamp, | | C_comp_gnd_clamp | | Vmeas, Cref, Rref, Vref | | Rref_diff, Cref_diff | | ------- | | | | | |-- [Model Spec] Vinh, Vinl, Vinh+, Vinh-, Vinl+, | | | Vinl-, S_overshoot_high, | | | S_overshoot_low, D_overshoot_high, | | | D_overshoot_low, D_overshoot_time, | | | Pulse_high, Pulse_low, Pulse_time, | | | Vmeas, Cref, Rref, Cref_rising, | | | Cref_falling, Rref_rising, | | | Rref_falling, Vref_rising, | | | Vref_falling, Vmeas_rising, | | | Vmeas_falling, | | | Rref_diff, Cref_diff | | |-- [Receiver Thresholds] Vth, Vth_min, Vth_max, Vinh_ac, | | | Vinh_dc, Vinl_ac, Vinl_dc, | | | Threshold_sensitivity, | | | Reference_supply, Vcross_low, | | | Vcross_high, Vdiff_ac, Vdiff_dc, | | | Tslew_ac, Tdiffslew_ac | | |-- [Add Submodel] | | |-- [Driver Schedule] | | |-- [Temperature Range] | | |-- [Voltage Range] | | |-- [Pullup Reference] | | |-- [Pulldown Reference] | | |-- [POWER Clamp Reference] | | |-- [GND Clamp Reference] | | |-- [External Reference] | | |-- [TTgnd] | | |-- [TTpower] | | |-- [Pulldown] | | |-- [Pullup] | | |-- [GND Clamp] | | |-- [POWER Clamp] | | |-- [Rgnd] | | |-- [Rpower] | | |-- [Rac] | | |-- [Cac] | | |-- [On] | | |-- [Off] | | |-- [R Series] | | |-- [L Series] | | |-- [Rl Series] | | |-- [C Series] | | |-- [Lc Series] | | |-- [Rc Series] | | |-- [Series Current] | | |-- [Series MOSFET] Vds | | |-- [Ramp] dV/dt_r, dV/dt_f, | | | R_load | | |-- [Rising Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut | | |-- [Falling Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut | | |-- [Test Data] Test_data_type *, Driver_model, | | | Driver_model_inv, Test_load | | | ----------- | | | |--[Rising Waveform Near] | | | |--[Falling Waveform Near] | | | |--[Rising Waveform Far] | | | |--[Falling Waveform Far] | | | |--[Diff Rising Waveform Near] | | | |--[Diff Falling Waveform Near] | | | |--[Diff Rising Waveform Far] | | | |--[Diff Falling Waveform Far] | | | |--[Test Load] Test_load_type, C1_near, Rs_near, | | | Ls_near, C2_near, Rp1_near, | | | Rp2_near, Td, Zo, Rp1_far, Rp2_far, | | | C2_far, L2_far, Rs_far, C1_far, | | | V_term1, V_term2, Receiver_model, | | | Receiver_model_inv, R_diff_near, | | | R_diff_far | | | | | |-- [External Model] Language, Corner, Parameters, Ports | | | D_to_A, A_to_D | | | ---------- | | | |-- [End External Model] | | | **| | |-- [Add Submodel] | | | | | | | |-- [Submodel] Submodel_type | | ---------- | | |-- [Submodel Spec] V_trigger_r, V_trigger_f, Off_delay | | |-- [POWER Pulse Table] | | |-- [GND Pulse Table] | | |-- [Pulldown] | | |-- [Pullup] | | |-- [GND Clamp] | | |-- [POWER Clamp] | | |-- [Ramp] dV/dt_r, dV/dt_f, R_load | | |-- [Rising Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut | | |-- [Falling Waveform] R_fixture, V_fixture, | | | V_fixture_min, V_fixture_max, | | | C_fixture, L_fixture, R_dut, L_dut, | | | C_dut | | | | | |-- [External Circuit] Language, Corner, Parameters, Ports | | D_to_A, A_to_D | | ---------- | | |-- [End External Circuit] | | | | | | | |-- [Define Package Model] | | ---------------------- | | |-- [Manufacturer] | | |-- [OEM] | | |-- [Description] | | |-- [Number Of Sections] | | |-- [Number Of Pins] | | |-- [Pin Numbers] | | | Len , L , R , C , | | | Fork , Endfork | | |-- [Model Data] | | | ------------ | | | |-- [Resistance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | ------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [Inductance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | ------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [Capacitance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | -------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [End Model Data] | | |-- [End Package Model] | | ** Line removed | | | |-- [End] | | |.pkg FILE |--------- | |-- File Data Header | | ----------------- | | |-- [IBIS Ver] | | |-- [Comment Char] | | |-- [File Name] | | |-- [File Rev] | | |-- [Date] | | |-- [Source] | | |-- [Notes] | | |-- [Disclaimer] | | |-- [Copyright] | | | |-- [Define Package Model] | | ---------------------- | | |-- [Manufacturer] | | |-- [OEM] | | |-- [Description] | | |-- [Number Of Sections] | | |-- [Number Of Pins] | | |-- [Pin Numbers] | | | Len , L , C , R , | | | Fork , Endfork | | |-- [Model Data] | | | ------------ | | | |-- [Resistance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | ------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [Inductance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | ------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [Capacitance Matrix] Banded_matrix, Sparse_matrix, | | | | Full_matrix | | | | -------------------- | | | | |-- [Bandwidth] | | | | |-- [Row] | | | |-- [End Model Data] | | |-- [End Package Model] | | | |-- [End] | | |.ebd FILE |--------- | |-- File Data Section | | ----------------- | | |-- [IBIS Ver] | | |-- [Comment Char] | | |-- [File Name] | | |-- [File Rev] | | |-- [Date] | | |-- [Source] | | |-- [Notes] | | |-- [Disclaimer] | | |-- [Copyright] | | | |-- [Begin Board Description] | | ---------------------- | | |-- [Manufacturer] | | |-- [Number of Pins] | | |-- [Pin List] signal_name | | |-- [Path Description] Len , L , R , C , | | | Fork , Endfork , | | | Pin , Node | | |-- [Reference Designator Map] | | |-- [End Board Description] | | | |-- [End] |============================================================================= |============================================================================= Additionally, Section 6b requires a minor change to Figure 1. The old text is shown below: | | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] | | |-- [End External Model] | | | ... | | ... | |-- [External Circuit] | |-- [End External Circuit] | | ... | This should be changed to: | | The placement of these keywords within the hierarchy of IBIS is shown in the | following diagram: | | | |-- [Component] | | | ... | | |-- [Node Declarations] |* | | --------- |* | | |-- [End Node Declarations] | | | ... | | | ... | | |-- [Circuit Call] |* | | --------- |* | | |-- [End Circuit Call] | | | ... | | ... | |-- [Model] | | | ... | | |-- [External Model] |* | ---------- |* | |-- [End External Model] | | ... | |-- [External Circuit] |* | ---------- |* | |-- [End External Circuit] | | | | ... | ***************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION: Tree hierarchy diagrams have been created for revisions of the IBIS specification since version 3.0. To date, no hierarchy tree has ever been formally ratified or approved by the IBIS Open Forum. Revisions to the hierarchy should be made as new keywords are added to the specification. BIRD89.1 Text revised to place [Add Submodel] within the scope of [Model]. ***************************************************************************** ANY OTHER BACKGROUND INFORMATION: *****************************************************************************