****************************************************************************** ****************************************************************************** BUFFER ISSUE RESOLUTION DOCUMENT (BIRD) BIRD ID#: 91.3 ISSUE TITLE: Multi-lingual Logic States Clarification REQUESTOR: Ian Dodd and John Angulo, Mentor Graphics Corp. DATE SUBMITTED: August 26, 2004 DATE REVISED: October 4, 2004; October 26, 2004 DATE ACCEPTED BY IBIS OPEN FORUM: November 19, 2004 ****************************************************************************** ****************************************************************************** STATEMENT OF THE ISSUE: Descriptions of the D_to_A and A_to_D subparameters under [External Model] and [External Circuit] keywords mention the allowed logic states for the D_receive, D_drive, D_enable and D_switch ports. However, the existing text does not refer to definitions of the allowed states in VHDL-AMS or Verilog-AMS specification documents, and does not discuss the allowed states outside of D_to_A and A_to_D subparameters. The text also omits any required types of either digital or analog ports in the AMS model. This BIRD addresses these omissions. BIRD 91.1: Choice of words improved in the paragraphs specifying restrictions on port types and values. BIRD 91.2: The paragraphs that were to have been inserted under the [External Model] and [External Circuit] keywords are consolidated and relocated to the GENERAL ASSUMPTIONS part of Section 6b. ****************************************************************************** STATEMENT OF THE RESOLVED SPECIFICATIONS: In Section 6b, under LANGUAGES SUPPORTED, replace the paragraph: | In addition the "IEEE Standard Multivalue Logic System for VHDL Model | Interoperability (Std_logic_1164)" designated IEEE Std. 1164-1993 is | required to promote common digital data types. | with this paragraph: | In addition the "IEEE Standard Multivalue Logic System for VHDL Model | Interoperability (Std_logic_1164)", designated IEEE Std. 1164-1993, is | required to promote common digital data types for IBIS files referencing | VHDL-AMS. Also, the Accellera Verilog-AMS Language Reference Manual | Version 2.2 is required to promote common digital data types for IBIS | files referencing Verilog-AMS. In Section 6b, change the subsection titled SPICE versus VHDL-AMS and Verilog-AMS under GENERAL ASSUMPTIONS from: | SPICE versus VHDL-AMS and VERILOG-AMS | | The intent of native IBIS is to model the circuit block between the region | where analog signals are of interest, and the digital logic domain internal | to the component. (for the purposes of this discussion, the IBIS circuit | block is called a "model unit" in the drawings and document text below). | | The multi-lingual modeling extensions maintain and expand this approach, | assuming that both digital signals and/or analog signals can move to and | from the model unit. All VHDL-AMS and Verilog-AMS models, therefore must | have digital ports and analog ports (in certain cases, digital ports may not | be required, as in the case of interconnects; see [External Circuit] | below). Routines to convert signals from one format to the other are the | responsibility of the model author. | | SPICE cannot process digital signals. All SPICE input and output signals | must be in analog format. Consequently, IBIS multi-lingual models using | SPICE require analog-to-digital (A_to_D) and/or digital-to-analog (D_to_A) | converters to be provided by the EDA tool. The converter subparameters are | declared by the user, as part of the [External Model] or [External Circuit] | syntax, with user-defined names for the ports which connect the converters | to the analog ports of the SPICE model. The details behind these | declarations are explained in the keyword definitions below. | | To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed to | ensure that a model unit consists of only digital ports and/or analog ports. | SPICE, however, needs extra data conversion, provided by the EDA tool, to | ensure that any digital signals can be correctly processed. To: | Port types and states: | | The intent of native IBIS is to model the circuit block between the region | where analog signals are of interest, and the digital logic domain internal | to the component. For the purposes of this discussion, the IBIS circuit | block is called a "model unit" in the drawings and document text below. | | The multi-lingual modeling extensions maintain and expand this approach, | assuming that both digital signals and/or analog signals can move to and | from the model unit. All VHDL-AMS and Verilog-AMS models, therefore must | have digital ports and analog ports. In certain cases, digital ports may not | be required, as in the case of interconnects; see [External Circuit] | below. Routines to convert signals from one format to the other are the | responsibility of the model author. | |** Digital ports under AMS languages must follow certain constraints on type |** and state. In VHDL-AMS models, analog ports must have type "electrical". | Digital ports must have type "std_logic" as defined in IEEE Standard | Multivalue Logic System for VHDL Model Interoperability (Std_logic_1164). | In Verilog-AMS models, analog ports must be of discipline "electrical" or a | subdiscipline thereof. Digital ports must be of discipline "logic" as | defined in the Accellera Verilog-AMS Language Reference Manual Version 2.2 | and be constrained to states as defined in IEEE Std. 1164-1993. | |* The digital ports delivering signals to the AMS model, D_drive, D_enable, and |* D_switch, must be limited to the '1' or '0' states for VHDL-AMS, or, |* equivalently, to the 1 or 0 states for Verilog-AMS. The D_receive digital |* port may only have the '1', '0', or 'X' states in VHDL-AMS, or, equivalently, |* the 1, 0, or X states in Verilog-AMS. All digital ports other than the |* foregoing predefined ports may use any of the logic states allowed by IEEE |* Std. 1164-1993. | | SPICE versus VHDL-AMS and VERILOG-AMS | | SPICE cannot process digital signals. All SPICE input and output signals | must be in analog format. Consequently, IBIS multi-lingual models using | SPICE require analog-to-digital (A_to_D) and/or digital-to-analog (D_to_A) | converters to be provided by the EDA tool. The converter subparameters are | declared by the user, as part of the [External Model] or [External Circuit] | syntax, with user-defined names for the ports which connect the converters | to the analog ports of the SPICE model. The details behind these | declarations are explained in the keyword definitions below. | | To summarize, Verilog-AMS and VHDL-AMS contain all the capability needed to | ensure that a model unit consists of only digital ports and/or analog ports. | SPICE, however, needs extra data conversion, provided by the EDA tool, to | ensure that any digital signals can be correctly processed. ****************************************************************************** ANALYSIS PATH/DATA THAT LED TO SPECIFICATION The present specification discusses the meaning of ports within the [External Model] and [External Circuit] keywords, but does not specify how they must be defined in the underlying VHDL-AMS or Verilog-AMS languages to ensure usability by EDA tools. The allowed values of digital ports also must be defined so that tools may use them reliably. BIRD 91.1: Choice of words improved in the paragraphs specifying restrictions on port types and values. BIRD 91.2: Because the digital port type and state rules are essentially the same for both [External Model] and [External Circuit], consolidating the paragraphs in a single location may simplify the document. ****************************************************************************** ANY OTHER BACKGROUND INFORMATION: BIRD91.2 was approved and issued as BIRD91.3 with two minor stylistic changes proposed and accepted at the November 19, 2004 IBIS Open Forum meeting. ****************************************************************************** ******************************************************************************